TR201917294A2 - Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ - Google Patents
Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ Download PDFInfo
- Publication number
- TR201917294A2 TR201917294A2 TR2019/17294A TR201917294A TR201917294A2 TR 201917294 A2 TR201917294 A2 TR 201917294A2 TR 2019/17294 A TR2019/17294 A TR 2019/17294A TR 201917294 A TR201917294 A TR 201917294A TR 201917294 A2 TR201917294 A2 TR 201917294A2
- Authority
- TR
- Turkey
- Prior art keywords
- reversible
- cmos circuits
- simultaneous faults
- detection
- doors
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title abstract 2
- 230000002441 reversible effect Effects 0.000 title abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 230000000873 masking effect Effects 0.000 abstract 1
- 230000001360 synchronised effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/319—Tester hardware, i.e. output processing circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
Buluş, tersinir ve korunumlu kapılar kullanılarak eşzamanlı (çevrimiçi) hataların CMOS devrelerde %100 tespitini sağlayan bir yöntem ile ilgilidir. Söz konusu yöntem ile CMOS devrelerinde oluşan hatalar maskelenmeden tespit edilebilmektedir.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TR2019/17294A TR201917294A2 (tr) | 2019-11-07 | 2019-11-07 | Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ |
US17/092,352 US11307252B2 (en) | 2019-11-07 | 2020-11-09 | Perfect detection of concurrent faults in CMOS circuits by exploiting reversible and preservative gates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TR2019/17294A TR201917294A2 (tr) | 2019-11-07 | 2019-11-07 | Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ |
Publications (1)
Publication Number | Publication Date |
---|---|
TR201917294A2 true TR201917294A2 (tr) | 2021-05-21 |
Family
ID=75846522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TR2019/17294A TR201917294A2 (tr) | 2019-11-07 | 2019-11-07 | Tersi̇ni̇r ve korunumlu kapilardan yararlanilarak cmos devrelerde oluşan eş zamanli hatalarin tamami̇yle tespi̇ti̇ |
Country Status (2)
Country | Link |
---|---|
US (1) | US11307252B2 (tr) |
TR (1) | TR201917294A2 (tr) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1004381B (it) | 1974-03-15 | 1976-07-10 | Sie Soc It Elettronica | Dispositivo elettronico bistabile verificabile durante il servizio |
JPS6029680A (ja) | 1983-07-27 | 1985-02-15 | Toshiba Corp | Cmos論理回路の試験方法 |
EP0249119A1 (de) | 1986-06-10 | 1987-12-16 | Siemens Aktiengesellschaft | Aufwandsreduzierte Antivalenz-und Äquivalenz-Gatterschaltung zur Verwendung in aktiven Testhilfen für Schaltungsanordnungen in CMOS-Technik |
JPH11145800A (ja) | 1997-11-10 | 1999-05-28 | Toshiba Corp | Cmos型可変遅延回路及びその遅延時間の制御方法並びに半導体試験装置 |
KR100360717B1 (ko) | 2000-03-27 | 2002-11-13 | 김강철 | Cmos논리회로의 고장감지장치 |
-
2019
- 2019-11-07 TR TR2019/17294A patent/TR201917294A2/tr unknown
-
2020
- 2020-11-09 US US17/092,352 patent/US11307252B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20210141015A1 (en) | 2021-05-13 |
US11307252B2 (en) | 2022-04-19 |
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