SG93191A1 - Multi-chip chip-scale integrated circuit package - Google Patents
Multi-chip chip-scale integrated circuit packageInfo
- Publication number
- SG93191A1 SG93191A1 SG9900245A SG1999000245A SG93191A1 SG 93191 A1 SG93191 A1 SG 93191A1 SG 9900245 A SG9900245 A SG 9900245A SG 1999000245 A SG1999000245 A SG 1999000245A SG 93191 A1 SG93191 A1 SG 93191A1
- Authority
- SG
- Singapore
- Prior art keywords
- chip
- integrated circuit
- circuit package
- scale integrated
- scale
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG9900245A SG93191A1 (en) | 1999-01-28 | 1999-01-28 | Multi-chip chip-scale integrated circuit package |
KR1019990002950A KR20000052097A (en) | 1999-01-28 | 1999-01-29 | Multi-chip chip scale integrated circuit package |
JP11022261A JP2000223649A (en) | 1999-01-28 | 1999-01-29 | Chip scale ic package for multichip |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG9900245A SG93191A1 (en) | 1999-01-28 | 1999-01-28 | Multi-chip chip-scale integrated circuit package |
KR1019990002950A KR20000052097A (en) | 1999-01-28 | 1999-01-29 | Multi-chip chip scale integrated circuit package |
JP11022261A JP2000223649A (en) | 1999-01-28 | 1999-01-29 | Chip scale ic package for multichip |
Publications (1)
Publication Number | Publication Date |
---|---|
SG93191A1 true SG93191A1 (en) | 2002-12-17 |
Family
ID=28045990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG9900245A SG93191A1 (en) | 1999-01-28 | 1999-01-28 | Multi-chip chip-scale integrated circuit package |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2000223649A (en) |
KR (1) | KR20000052097A (en) |
SG (1) | SG93191A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6491751B1 (en) | 1998-09-18 | 2002-12-10 | Texas Industries, Inc. | Method for manufacturing cement using a raw material mix including finely ground steel slag |
KR20020020088A (en) * | 2000-09-07 | 2002-03-14 | 마이클 디. 오브라이언 | semiconductor package and its manufacturing method |
KR100508261B1 (en) * | 2000-10-04 | 2005-08-18 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package and method for manufacturing the same |
KR20030015553A (en) * | 2001-08-16 | 2003-02-25 | 강남석 | Aesthetic pack composition and manufacturing method thereof |
KR100481706B1 (en) * | 2002-03-25 | 2005-04-11 | 주식회사 넥사이언 | Method of fabricating flip chip |
US10615151B2 (en) | 2016-11-30 | 2020-04-07 | Shenzhen Xiuyuan Electronic Technology Co., Ltd | Integrated circuit multichip stacked packaging structure and method |
TWI626723B (en) * | 2017-03-06 | 2018-06-11 | 力成科技股份有限公司 | Package structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0890989A1 (en) * | 1997-01-24 | 1999-01-13 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing thereof |
-
1999
- 1999-01-28 SG SG9900245A patent/SG93191A1/en unknown
- 1999-01-29 JP JP11022261A patent/JP2000223649A/en active Pending
- 1999-01-29 KR KR1019990002950A patent/KR20000052097A/en not_active Application Discontinuation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0890989A1 (en) * | 1997-01-24 | 1999-01-13 | Rohm Co., Ltd. | Semiconductor device and method for manufacturing thereof |
Also Published As
Publication number | Publication date |
---|---|
KR20000052097A (en) | 2000-08-16 |
JP2000223649A (en) | 2000-08-11 |
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