SG153683A1 - 3d integrated circuit package and method of fabrication thereof - Google Patents

3d integrated circuit package and method of fabrication thereof

Info

Publication number
SG153683A1
SG153683A1 SG200718742-0A SG2007187420A SG153683A1 SG 153683 A1 SG153683 A1 SG 153683A1 SG 2007187420 A SG2007187420 A SG 2007187420A SG 153683 A1 SG153683 A1 SG 153683A1
Authority
SG
Singapore
Prior art keywords
wafer
elements
die
integrated circuits
locations
Prior art date
Application number
SG200718742-0A
Inventor
Sangki Hong
Subhash Gupta
Original Assignee
Tezzaron Semiconductor S Pte L
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tezzaron Semiconductor S Pte L filed Critical Tezzaron Semiconductor S Pte L
Priority to SG200718742-0A priority Critical patent/SG153683A1/en
Priority to PCT/SG2008/000481 priority patent/WO2009078816A1/en
Publication of SG153683A1 publication Critical patent/SG153683A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A method of fabricating a 3D integrated circuit structure comprising the steps of: providing a wafer having a plurality of wafer integrated circuits formed thereon, each of said wafer integrated circuits being provided with a plurality of wafer contact elements; providing a plurality of die elements, each of said die elements being configured to be connected electrically to one of said wafer integrated circuits, said die elements each having a plurality of die contact elements; with the die elements at respective predetermined locations on the surface of the wafer the locations of the die contact elements corresponding to locations of said wafer contact elements of the wafer integrated circuits; providing a positioning member in predetermined juxtaposition with said wafer, the positioning member having a plurality of formations at locations of the positioning member corresponding to locations of said plurality of wafer integrated circuits, said formations defining respective sets of lateral boundaries arranged to constrain movement of respective die elements when provided on said wafer such that respective corresponding contact elements of the wafer integrated circuits and die elements are aligned with one another, the method further comprising the step of placing each one of a plurality of die elements on said wafer within one of a set of respective lateral boundaries defined by said formations, and bonding said die elements to said wafer.
SG200718742-0A 2007-12-14 2007-12-14 3d integrated circuit package and method of fabrication thereof SG153683A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SG200718742-0A SG153683A1 (en) 2007-12-14 2007-12-14 3d integrated circuit package and method of fabrication thereof
PCT/SG2008/000481 WO2009078816A1 (en) 2007-12-14 2008-12-15 3d integrated circuit package and method of fabrication thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200718742-0A SG153683A1 (en) 2007-12-14 2007-12-14 3d integrated circuit package and method of fabrication thereof

Publications (1)

Publication Number Publication Date
SG153683A1 true SG153683A1 (en) 2009-07-29

Family

ID=40795778

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200718742-0A SG153683A1 (en) 2007-12-14 2007-12-14 3d integrated circuit package and method of fabrication thereof

Country Status (2)

Country Link
SG (1) SG153683A1 (en)
WO (1) WO2009078816A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11599299B2 (en) 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8544165B2 (en) 2010-03-29 2013-10-01 Hong Kong Applied Science & Technology Research Institute Co., Ltd. Apparatus for aligning electronic components
CN102664159B (en) * 2012-03-31 2014-09-24 华中科技大学 Multi-chip alignment method and device thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW501215B (en) * 2000-10-18 2002-09-01 Scs Hightech Inc Method and apparatus for multiple known good die processing
US20050015970A1 (en) * 2003-06-12 2005-01-27 Matrics, Inc. Method, system, and apparatus for transfer of dies using a pin plate
SG119230A1 (en) * 2004-07-29 2006-02-28 Micron Technology Inc Interposer including at least one passive element at least partially defined by a recess formed therein method of manufacture system including same and wafer-scale interposer
US7226821B2 (en) * 2005-06-24 2007-06-05 Cardiac Pacemakers, Inc. Flip chip die assembly using thin flexible substrates

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11599299B2 (en) 2019-11-19 2023-03-07 Invensas Llc 3D memory circuit

Also Published As

Publication number Publication date
WO2009078816A1 (en) 2009-06-25

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