SG115609A1 - A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structure - Google Patents
A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structureInfo
- Publication number
- SG115609A1 SG115609A1 SG200400364A SG200400364A SG115609A1 SG 115609 A1 SG115609 A1 SG 115609A1 SG 200400364 A SG200400364 A SG 200400364A SG 200400364 A SG200400364 A SG 200400364A SG 115609 A1 SG115609 A1 SG 115609A1
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor structure
- fabricating
- insulator
- crystalline layer
- strained crystalline
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP03290231A EP1443550A1 (en) | 2003-01-29 | 2003-01-29 | A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structure |
| US48599703P | 2003-07-09 | 2003-07-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG115609A1 true SG115609A1 (en) | 2005-10-28 |
Family
ID=33542570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG200400364A SG115609A1 (en) | 2003-01-29 | 2004-01-28 | A method for fabricating a strained crystalline layer on an insulator, a semiconductor structure therefor, and a fabricated semiconductor structure |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP4853990B2 (en) |
| KR (1) | KR100576684B1 (en) |
| CN (1) | CN1282990C (en) |
| SG (1) | SG115609A1 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10310740A1 (en) * | 2003-03-10 | 2004-09-30 | Forschungszentrum Jülich GmbH | Method for producing a stress-relaxed layer structure on a non-lattice-matched substrate, and use of such a layer system in electronic and / or optoelectronic components |
| FR2880988B1 (en) * | 2005-01-19 | 2007-03-30 | Soitec Silicon On Insulator | TREATMENT OF A LAYER IN SI1-yGEy TAKEN |
| FR2889887B1 (en) * | 2005-08-16 | 2007-11-09 | Commissariat Energie Atomique | METHOD FOR DEFERING A THIN LAYER ON A SUPPORT |
| FR2891281B1 (en) * | 2005-09-28 | 2007-12-28 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING A THIN FILM ELEMENT |
| US7608526B2 (en) * | 2006-07-24 | 2009-10-27 | Asm America, Inc. | Strained layers within semiconductor buffer structures |
| GB2467935B (en) * | 2009-02-19 | 2013-10-30 | Iqe Silicon Compounds Ltd | Formation of thin layers of GaAs and germanium materials |
| FR2972567B1 (en) * | 2011-03-09 | 2013-03-22 | Soitec Silicon On Insulator | METHOD OF FORMING A STRUCTURE OF GE ON III / V ON INSULATION |
| CN103165511B (en) * | 2011-12-14 | 2015-07-22 | 中国科学院上海微***与信息技术研究所 | Method for manufacturing germanium on insulator (GOI) |
| JP6726180B2 (en) * | 2014-11-18 | 2020-07-22 | グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． | High resistivity semiconductor-on-insulator wafer and manufacturing method |
-
2004
- 2004-01-27 JP JP2004018825A patent/JP4853990B2/en not_active Expired - Lifetime
- 2004-01-28 SG SG200400364A patent/SG115609A1/en unknown
- 2004-01-28 KR KR1020040005279A patent/KR100576684B1/en active IP Right Grant
- 2004-01-29 CN CNB2004100033711A patent/CN1282990C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR20040070018A (en) | 2004-08-06 |
| KR100576684B1 (en) | 2006-05-04 |
| CN1538499A (en) | 2004-10-20 |
| JP2004343052A (en) | 2004-12-02 |
| JP4853990B2 (en) | 2012-01-11 |
| CN1282990C (en) | 2006-11-01 |
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