SG11202003151VA - Etching method and semiconductor manufacturing method - Google Patents

Etching method and semiconductor manufacturing method

Info

Publication number
SG11202003151VA
SG11202003151VA SG11202003151VA SG11202003151VA SG11202003151VA SG 11202003151V A SG11202003151V A SG 11202003151VA SG 11202003151V A SG11202003151V A SG 11202003151VA SG 11202003151V A SG11202003151V A SG 11202003151VA SG 11202003151V A SG11202003151V A SG 11202003151VA
Authority
SG
Singapore
Prior art keywords
semiconductor manufacturing
etching
etching method
semiconductor
manufacturing
Prior art date
Application number
SG11202003151VA
Inventor
Yosuke Tanimoto
Original Assignee
Showa Denko Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko Kk filed Critical Showa Denko Kk
Publication of SG11202003151VA publication Critical patent/SG11202003151VA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • H01L21/31116Etching inorganic layers by chemical means by dry-etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
SG11202003151VA 2017-11-02 2018-10-22 Etching method and semiconductor manufacturing method SG11202003151VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017212871 2017-11-02
PCT/JP2018/039220 WO2019087850A1 (en) 2017-11-02 2018-10-22 Etching method and semiconductor manufacturing method

Publications (1)

Publication Number Publication Date
SG11202003151VA true SG11202003151VA (en) 2020-05-28

Family

ID=66331838

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202003151VA SG11202003151VA (en) 2017-11-02 2018-10-22 Etching method and semiconductor manufacturing method

Country Status (9)

Country Link
US (1) US11114305B2 (en)
EP (1) EP3706158A4 (en)
JP (1) JP7310608B2 (en)
KR (1) KR102376841B1 (en)
CN (1) CN111213224B (en)
IL (1) IL274331B2 (en)
SG (1) SG11202003151VA (en)
TW (1) TWI713920B (en)
WO (1) WO2019087850A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113784776B (en) * 2019-08-06 2024-03-19 株式会社力森诺科 Gas treatment method and gas treatment apparatus
CN115699266A (en) * 2020-08-31 2023-02-03 昭和电工株式会社 Plasma etching method and method for manufacturing semiconductor element
WO2023100476A1 (en) * 2021-12-02 2023-06-08 株式会社レゾナック Method for forming deposition film

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US176293A (en) 1876-04-18 Improvement in grain-binders
US152255A (en) 1874-06-23 Improvement in transplanters
JPH01304731A (en) * 1988-06-01 1989-12-08 Matsushita Electric Ind Co Ltd Etching method, etched mirror and etching apparatus
JP3160961B2 (en) * 1991-10-02 2001-04-25 ソニー株式会社 Dry etching method
US6660643B1 (en) * 1999-03-03 2003-12-09 Rwe Schott Solar, Inc. Etching of semiconductor wafer edges
JP2010041028A (en) * 2008-07-11 2010-02-18 Tokyo Electron Ltd Substrate processing method
CN101625966A (en) 2008-07-11 2010-01-13 东京毅力科创株式会社 Substrate processing method
SG173283A1 (en) 2010-01-26 2011-08-29 Semiconductor Energy Lab Method for manufacturing soi substrate
JP2014041849A (en) 2010-06-24 2014-03-06 Nippon Zeon Co Ltd Gas for plasma reaction and its utilization
JP5537324B2 (en) 2010-08-05 2014-07-02 株式会社東芝 Manufacturing method of semiconductor device
US20150357200A1 (en) 2012-12-27 2015-12-10 Zeon Corporation Dry etching method
JP6788177B2 (en) * 2015-05-14 2020-11-25 セントラル硝子株式会社 Dry etching method, dry etching agent and semiconductor device manufacturing method
JP6327295B2 (en) 2015-08-12 2018-05-23 セントラル硝子株式会社 Dry etching method
JP6604833B2 (en) 2015-12-03 2019-11-13 東京エレクトロン株式会社 Plasma etching method

Also Published As

Publication number Publication date
CN111213224B (en) 2023-12-19
EP3706158A4 (en) 2021-01-06
KR102376841B1 (en) 2022-03-18
EP3706158A1 (en) 2020-09-09
KR20200044974A (en) 2020-04-29
WO2019087850A1 (en) 2019-05-09
US11114305B2 (en) 2021-09-07
IL274331B (en) 2022-12-01
IL274331B2 (en) 2023-04-01
US20210217627A1 (en) 2021-07-15
JP7310608B2 (en) 2023-07-19
CN111213224A (en) 2020-05-29
IL274331A (en) 2020-06-30
TWI713920B (en) 2020-12-21
TW201930648A (en) 2019-08-01
JPWO2019087850A1 (en) 2020-09-24

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