SG11201909120PA - Constructing parity check matrices with row-orthogonality for rate compatible qc-ldpc codes - Google Patents
Constructing parity check matrices with row-orthogonality for rate compatible qc-ldpc codesInfo
- Publication number
- SG11201909120PA SG11201909120PA SG11201909120PA SG11201909120PA SG 11201909120P A SG11201909120P A SG 11201909120PA SG 11201909120P A SG11201909120P A SG 11201909120PA SG 11201909120P A SG11201909120P A SG 11201909120PA
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- parity check
- row
- check matrix
- ldpc
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1131—Scheduling of bit node or check node processing
- H03M13/114—Shuffled, staggered, layered or turbo decoding schedules
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/615—Use of computational or mathematical techniques
- H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
- H03M13/618—Shortening and extension of codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/6306—Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission, e.g. coding schemes for the multiple transmission of the same information or the transmission of incremental redundancy
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/63—Joint error correction and other techniques
- H03M13/635—Error control coding in combination with rate matching
- H03M13/6362—Error control coding in combination with rate matching by puncturing
- H03M13/6368—Error control coding in combination with rate matching by puncturing using rate compatible puncturing or complementary puncturing
- H03M13/6393—Rate compatible low-density parity check [LDPC] codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6561—Parallelized implementations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0067—Rate matching
- H04L1/0068—Rate matching by puncturing
- H04L1/0069—Puncturing patterns
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1812—Hybrid protocols; Hybrid automatic repeat request [HARQ]
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- Engineering & Computer Science (AREA)
- Probability & Statistics with Applications (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Algebra (AREA)
- Computing Systems (AREA)
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
OO O O (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 15 November 2018 (15.11.2018) ill Hu omits I io 10 0101011011011111 OM REHM 011 (10) International Publication Number WO 2018/209035 Al WIPO I PCT (51) International Patent Classification: H03M 13/11 (2006.01) (21) International Application Number: PCT/US2018/031988 (22) International Filing Date: 10 May 2018 (10.05.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 62/505,573 12 May 2017 (12.05.2017) US 15/975,440 09 May 2018 (09.05.2018) US (71) Applicant: QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration, 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (72) Inventor: RICHARDSON, Thomas; 5775 Morehouse Drive, San Diego, California 92121-1714 (US). (74) Agent: KENT, Preston E. et al.; Patterson & Sheridan, L.L.P., 24 Greenway Plaza, Suite 1600, Houston, Texas 77046-2472 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (54) Title: CONSTRUCTING PARITY CHECK MATRICES WITH ROW-ORTHOGONALITY FOR RATE COMPATIBLE QC- LDPC CODES 1400 r 1402 RECEIVE SOFT BITS ASSOCIATED TO AN LDPC CODEWORD r 1404 PERFORM LDPC DECODING OF THE SOFT BITS USING A PARITY CHECK MATRIX, WHEREIN: EACH ROW OF THE PARITY CHECK MATRIX CORRESPONDS TO A LIFTED PARITY CHECK OF A LIFTED LDPC CODE, AT LEAST TWO COLUMNS OF THE PARITY CHECK MATRIX CORRESPOND TO PUNCTURED VARIABLE NODES OF THE LIFTED LDPC CODE, AND THE PARITY CHECK MATRIX HAS ROW ORTHOGONALITY BETWEEN EACH PAIR OF CONSECUTIVE ROWS THAT ARE BELOW A ROW TO WHICH THE AT LEAST TWO PUNCTURED VARIABLE NODES ARE BOTH CONNECTED FIG. 14 (57) : Certain aspects of the present disclosure generally relate to methods and apparatus for decoding quasi-cyclic low- density parity check (QC-LDPC) rate-compatible codes, for example, using a parity check matrix comprising first layers according to a high-rate core graph and second layers for HARQ transmission, where the parity check matrix has quasi row-orthogonality or full row-orthogonality within the second layers. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected. [Continued on next page] WO 2018/209035 Al MIDEDIMOMMIDIIMERIHNONIMOIMIOMMOVOIS (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Published: — with international search report (Art. 21(3))
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201762505573P | 2017-05-12 | 2017-05-12 | |
US15/975,440 US10680646B2 (en) | 2017-05-12 | 2018-05-09 | Row orthogonality in LDPC rate compatible design |
PCT/US2018/031988 WO2018209035A1 (en) | 2017-05-12 | 2018-05-10 | Constructing parity check matrices with row-orthogonality for rate compatible qc-ldpc codes |
Publications (1)
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SG11201909120PA true SG11201909120PA (en) | 2019-11-28 |
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SG11201909120P SG11201909120PA (en) | 2017-05-12 | 2018-05-10 | Constructing parity check matrices with row-orthogonality for rate compatible qc-ldpc codes |
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US (3) | US10680646B2 (en) |
EP (1) | EP3622627A1 (en) |
JP (1) | JP6828190B2 (en) |
KR (1) | KR102197173B1 (en) |
CN (2) | CN110622425B (en) |
BR (1) | BR112019023301A2 (en) |
SG (1) | SG11201909120PA (en) |
TW (1) | TWI725308B (en) |
WO (1) | WO2018209035A1 (en) |
Families Citing this family (11)
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US10680646B2 (en) | 2017-05-12 | 2020-06-09 | Qualcomm Incorporated | Row orthogonality in LDPC rate compatible design |
US10879927B2 (en) * | 2017-05-17 | 2020-12-29 | Futurewei Technologies, Inc. | Compact low density parity check (LDPC) base graph |
CN108988869B (en) * | 2017-05-31 | 2021-07-30 | 大唐移动通信设备有限公司 | Method and device for determining check matrix and computer storage medium |
US10312939B2 (en) | 2017-06-10 | 2019-06-04 | Qualcomm Incorporated | Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code |
CN111492586B (en) * | 2017-12-15 | 2022-09-09 | 华为技术有限公司 | Method and device for designing basic matrix of LDPC code with orthogonal rows |
WO2019164515A1 (en) * | 2018-02-23 | 2019-08-29 | Nokia Technologies Oy | Ldpc codes for 3gpp nr ultra-reliable low-latency communications |
US10979072B2 (en) * | 2019-03-19 | 2021-04-13 | Western Digital Technologies, Inc. | Punctured bit estimation and bit error rate estimation |
WO2020218629A1 (en) * | 2019-04-22 | 2020-10-29 | 엘지전자 주식회사 | Method for supporting rate-compatible non-binary ldpc code, and wireless terminal using same |
KR20210090483A (en) | 2020-01-10 | 2021-07-20 | 주식회사 엘지에너지솔루션 | Porous reduced graphene oxide, manufacturing method thereof, sulfur-carbon composite and lithium secondary battery comprising the same |
CN112039536B (en) * | 2020-06-12 | 2023-04-18 | 中山大学 | Adaptive polarization code coding and decoding method based on orthogonal frequency division multiplexing technology |
EP4309313A1 (en) * | 2021-03-18 | 2024-01-24 | Qualcomm Incorporated | Bit replacing for low density parity check encoding |
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TWI272777B (en) * | 2003-08-08 | 2007-02-01 | Intel Corp | Method and apparatus for varying lengths of low density parity check codewords |
KR100981500B1 (en) * | 2006-02-07 | 2010-09-10 | 삼성전자주식회사 | Low density parity check code-based hybrid automatic repeat request method |
US20070245217A1 (en) * | 2006-03-28 | 2007-10-18 | Stmicroelectronics S.R.L. | Low-density parity check decoding |
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US10680646B2 (en) | 2017-05-12 | 2020-06-09 | Qualcomm Incorporated | Row orthogonality in LDPC rate compatible design |
-
2018
- 2018-05-09 US US15/975,440 patent/US10680646B2/en active Active
- 2018-05-10 EP EP18732965.1A patent/EP3622627A1/en active Pending
- 2018-05-10 WO PCT/US2018/031988 patent/WO2018209035A1/en active Application Filing
- 2018-05-10 SG SG11201909120P patent/SG11201909120PA/en unknown
- 2018-05-10 JP JP2019561752A patent/JP6828190B2/en active Active
- 2018-05-10 CN CN201880030726.6A patent/CN110622425B/en active Active
- 2018-05-10 BR BR112019023301-6A patent/BR112019023301A2/en unknown
- 2018-05-10 TW TW107115891A patent/TWI725308B/en active
- 2018-05-10 CN CN202410167930.XA patent/CN118018038A/en active Pending
- 2018-05-10 KR KR1020197033238A patent/KR102197173B1/en active IP Right Grant
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2020
- 2020-05-05 US US16/867,330 patent/US11411581B2/en active Active
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2022
- 2022-08-05 US US17/817,717 patent/US11916571B2/en active Active
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BR112019023301A2 (en) | 2020-06-16 |
CN110622425A (en) | 2019-12-27 |
JP2020521362A (en) | 2020-07-16 |
EP3622627A1 (en) | 2020-03-18 |
US20230030277A1 (en) | 2023-02-02 |
US11411581B2 (en) | 2022-08-09 |
TW201902136A (en) | 2019-01-01 |
WO2018209035A1 (en) | 2018-11-15 |
CN118018038A (en) | 2024-05-10 |
KR20200003829A (en) | 2020-01-10 |
US20200266832A1 (en) | 2020-08-20 |
US10680646B2 (en) | 2020-06-09 |
TWI725308B (en) | 2021-04-21 |
KR102197173B1 (en) | 2020-12-31 |
US11916571B2 (en) | 2024-02-27 |
CN110622425B (en) | 2024-02-20 |
US20190013827A1 (en) | 2019-01-10 |
JP6828190B2 (en) | 2021-02-10 |
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