SG11201900437YA - Memory device, method of forming the same, method for controlling the same and memory array - Google Patents

Memory device, method of forming the same, method for controlling the same and memory array

Info

Publication number
SG11201900437YA
SG11201900437YA SG11201900437YA SG11201900437YA SG11201900437YA SG 11201900437Y A SG11201900437Y A SG 11201900437YA SG 11201900437Y A SG11201900437Y A SG 11201900437YA SG 11201900437Y A SG11201900437Y A SG 11201900437YA SG 11201900437Y A SG11201900437Y A SG 11201900437YA
Authority
SG
Singapore
Prior art keywords
international
memory device
nanyang
singapore
memory
Prior art date
Application number
SG11201900437YA
Inventor
Putu Andhita Dananjaya
Wen Siang Lew
Original Assignee
Univ Nanyang Tech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Nanyang Tech filed Critical Univ Nanyang Tech
Publication of SG11201900437YA publication Critical patent/SG11201900437YA/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0009—RRAM elements whose operation depends upon chemical change
    • G11C13/0011—RRAM elements whose operation depends upon chemical change comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8822—Sulfides, e.g. CuS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8416—Electrodes adapted for supplying ionic species

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Immobilizing And Processing Of Enzymes And Microorganisms (AREA)

Abstract

INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property 11111111111111111111111111111111111111111111111111111111111111111111111111111 Organization International Bureau (10) International Publication Number (43) International Publication Date .....0\"\" WO 2018/063093 Al 05 April 2018 (05.04.2018) WIP0 I PCT (51) International Patent Classification: (84) Designated States (unless otherwise indicated, for every H01L 45/00 (2006.01) HO1L 27/24 (2006.01) kind of regional protection available): ARIPO (BW, GH, Gll C 13/00 (2006.01) GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, (21) International Application Number: UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, PCT/SG2017/050457 TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, (22) International Filing Date: MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, 12 September 2017 (12.09.2017) TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). (25) Filing Language: English (26) Publication Language: English Published: (30) Priority Data: — with international search report (Art. 21(3)) 10201608151Q 29 September 2016 (29.09.2016) SG (71) Applicant: NANYANG TECHNOLOGICAL UNIVERSITY [SG/SG]; 50 Nanyang Avenue, Singapore 639798 (SG). (72) Inventors: DANANJAYA, Putu Andhita; c/o Nanyang Technological University, 50 Nanyang Avenue, Singapore - 639798 (SG). LEW, Wen Siang; c/o Nanyang Techno- logical University, 50 Nanyang Avenue, Singapore 639798 — (SG). = Agent: MCLAUGHLIN, Michael Gerard; Mclaughlin Ip = (74) Pte Ltd, 24a Mosque Street, Singapore 059504 (SG). = Designated States (unless otherwise indicated, for every = (81) kind of national protection available): AE, AG, AL, AM, = AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, = CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, = — HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, = = KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, = = SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, _ = TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. = = = (54) Title: MEMORY DEVICE, METHOD OF FORMING THE SAME, METHOD FOR CONTROLLING THE SAME AND MEM- - ORY ARRAY = — — (57) : According to embodiments of the present invention, a memory device is = 600b provided. The memory device includes an electrochemical metallization memory (ECM) k cell and a valence change memory (VCM) cell arranged one over the other. According to 631 further embodiments of the present invention, a method of forming a memory device, a — Il t__. Reactive Liccirmic tortilattic 1 632 ' method for controlling a memory device, and a memory array are also provided. en It, It PD C:r 0 = 04 u t. t tri,ta , - 602 M k A. --, I:isolator II 637 O • —.... `O+ - ,,,? — 0 x3 Sea%etittt. • :ketonic 438 Il 604 0 N FIG. 6D O
SG11201900437YA 2016-09-29 2017-09-12 Memory device, method of forming the same, method for controlling the same and memory array SG11201900437YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SG10201608151Q 2016-09-29
PCT/SG2017/050457 WO2018063093A1 (en) 2016-09-29 2017-09-12 Memory device, method of forming the same, method for controlling the same and memory array

Publications (1)

Publication Number Publication Date
SG11201900437YA true SG11201900437YA (en) 2019-02-27

Family

ID=61760036

Family Applications (2)

Application Number Title Priority Date Filing Date
SG11201900437YA SG11201900437YA (en) 2016-09-29 2017-09-12 Memory device, method of forming the same, method for controlling the same and memory array
SG10201912382TA SG10201912382TA (en) 2016-09-29 2017-09-12 Memory device, method of forming the same, method for controlling the same and memory array

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG10201912382TA SG10201912382TA (en) 2016-09-29 2017-09-12 Memory device, method of forming the same, method for controlling the same and memory array

Country Status (3)

Country Link
US (1) US20190272874A1 (en)
SG (2) SG11201900437YA (en)
WO (1) WO2018063093A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019161815A1 (en) * 2018-02-21 2019-08-29 Univerzita Pardubice A method of forming a metallic conductive filament and a random access memory device for carrying out the method
US11158788B2 (en) * 2018-10-30 2021-10-26 International Business Machines Corporation Atomic layer deposition and physical vapor deposition bilayer for additive patterning
US10885979B2 (en) * 2019-04-09 2021-01-05 International Business Machines Corporation Paired intercalation cells for drift migration
US11444125B2 (en) * 2020-06-17 2022-09-13 Globalfoundries Singapore Pte. Ltd. Memory devices and methods of forming memory devices
CN112490358A (en) * 2020-11-27 2021-03-12 西安交通大学 High-stability multi-resistance-state memristor based on series structure and preparation method thereof

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102449702B (en) * 2009-05-29 2015-05-20 于利奇研究中心有限公司 Memory element, stacking, memory matrix and method for operation
US20110084248A1 (en) * 2009-10-13 2011-04-14 Nanya Technology Corporation Cross point memory array devices
US8395926B2 (en) * 2010-06-18 2013-03-12 Sandisk 3D Llc Memory cell with resistance-switching layers and lateral arrangement
FR2973554B1 (en) * 2011-04-04 2013-04-12 Commissariat Energie Atomique "SELECTOR-TYPE ELECTRONIC DEVICE"
US9373786B1 (en) * 2013-01-23 2016-06-21 Adesto Technologies Corporation Two terminal resistive access devices and methods of formation thereof
US9425237B2 (en) * 2014-03-11 2016-08-23 Crossbar, Inc. Selector device for two-terminal memory

Also Published As

Publication number Publication date
WO2018063093A1 (en) 2018-04-05
SG10201912382TA (en) 2020-02-27
US20190272874A1 (en) 2019-09-05

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