SG11201509796WA - Automatically placed-and-routed adpll with pwm-based dco resolution ehhancement - Google Patents

Automatically placed-and-routed adpll with pwm-based dco resolution ehhancement

Info

Publication number
SG11201509796WA
SG11201509796WA SG11201509796WA SG11201509796WA SG11201509796WA SG 11201509796W A SG11201509796W A SG 11201509796WA SG 11201509796W A SG11201509796W A SG 11201509796WA SG 11201509796W A SG11201509796W A SG 11201509796WA SG 11201509796W A SG11201509796W A SG 11201509796WA
Authority
SG
Singapore
Prior art keywords
ehhancement
adpll
pwm
routed
automatically placed
Prior art date
Application number
SG11201509796WA
Inventor
Muhammad Faisal
David D Wentzloff
Original Assignee
Univ Michigan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Michigan filed Critical Univ Michigan
Publication of SG11201509796WA publication Critical patent/SG11201509796WA/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0997Controlling the number of delay elements connected in series in the ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/10Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • H03L7/103Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator the additional signal being a digital signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015Layout of the delay element
    • H03K2005/00234Layout of the delay element using circuits having two logic levels
    • H03K2005/00241Layout of the delay element using circuits having two logic levels using shift registers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06Phase locked loops with a controlled oscillator having at least two frequency control terminals
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50All digital phase-locked loop

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
SG11201509796WA 2013-05-31 2014-05-31 Automatically placed-and-routed adpll with pwm-based dco resolution ehhancement SG11201509796WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201361830045P 2013-05-31 2013-05-31
PCT/US2014/040426 WO2014194308A1 (en) 2013-05-31 2014-05-31 Automatically placed-and-routed adpll with pwm-based dco resolution ehhancement

Publications (1)

Publication Number Publication Date
SG11201509796WA true SG11201509796WA (en) 2015-12-30

Family

ID=51989456

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201509796WA SG11201509796WA (en) 2013-05-31 2014-05-31 Automatically placed-and-routed adpll with pwm-based dco resolution ehhancement

Country Status (4)

Country Link
US (1) US9515668B2 (en)
KR (1) KR20160013945A (en)
SG (1) SG11201509796WA (en)
WO (1) WO2014194308A1 (en)

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US9515668B2 (en) * 2013-05-31 2016-12-06 The Regents Of The University Of Michigan Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement
KR102210324B1 (en) * 2014-12-03 2021-02-01 삼성전자주식회사 Digital Phase-Locked Loop and Operating Method thereof
JP6481533B2 (en) * 2015-07-08 2019-03-13 株式会社デンソー Digitally controlled oscillator circuit
JP6584885B2 (en) * 2015-09-14 2019-10-02 株式会社東芝 Equipment with noise removal function
KR102546302B1 (en) * 2016-07-08 2023-06-21 삼성전자주식회사 Clock jitter measurement circuit and semiconductor device including the same
WO2018063231A1 (en) * 2016-09-29 2018-04-05 Intel IP Corporation Apparatus, system and method of generating a frequency output with a digitally controlled ring oscillator (dcro)
KR102608982B1 (en) 2016-12-26 2023-11-30 에스케이하이닉스 주식회사 All digital phase locked loop
US9954542B1 (en) 2017-02-01 2018-04-24 Apple Inc. Digital linearization technique for charge pump based fractional phased-locked loop
JP6844368B2 (en) * 2017-03-24 2021-03-17 セイコーエプソン株式会社 Time digital converter
TWI673957B (en) * 2018-08-27 2019-10-01 National Kaohsiung University Of Science And Technology Simplified time-to-digital conversion system and method thereof
CN110886415A (en) * 2019-08-22 2020-03-17 广东中集建筑制造有限公司 Modular curtain wall and mounting method thereof
KR20210042748A (en) * 2019-10-10 2021-04-20 삼성전자주식회사 A Phase-locked loop circuit and a clock generator including the same
US10911028B1 (en) * 2019-12-18 2021-02-02 Bae Systems Information And Electronic Systems Integration Inc. Phase adjustment preset for N-path filter
CN113054998B (en) * 2019-12-26 2023-04-18 澜至电子科技(成都)有限公司 Linear calibration system and method of time-to-digital converter and digital phase-locked loop
IL275511B2 (en) * 2020-06-18 2023-11-01 Capow Tech Ltd High-accuracy adaptive digital frequency synthesizer for wireless power systems
KR102430227B1 (en) * 2020-07-17 2022-08-08 고려대학교 산학협력단 Dual domain sub sampling phase lock loop
WO2022125188A2 (en) * 2020-10-14 2022-06-16 The Regents Of The University Of California Current-mismatch compensated charge pump for phase-locked loop applications
US11211936B1 (en) * 2021-01-05 2021-12-28 Taiwan Semiconductor Manufacturing Company, Ltd. Delay lock loop circuits and methods for operating same
JP7044184B2 (en) * 2021-02-12 2022-03-30 セイコーエプソン株式会社 Time digital converter

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US6603362B2 (en) * 2000-03-14 2003-08-05 Intersil Americas Inc. Subsampling digitizer-based frequency synthesizer
US7425874B2 (en) 2006-06-30 2008-09-16 Texas Instruments Incorporated All-digital phase-locked loop for a digital pulse-width modulator
US7812655B2 (en) * 2007-10-09 2010-10-12 Nokia Corporation Delay-locked loop control
KR101378299B1 (en) * 2009-12-18 2014-03-27 한국전자통신연구원 All digital phase locked loop
US8193845B2 (en) * 2010-07-06 2012-06-05 Microchip Technology Incorporated Binary-weighted delta-sigma fractional-N frequency synthesizer with digital-to-analog differentiators canceling quantization noise
US8248127B2 (en) * 2010-08-05 2012-08-21 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Digital phase lock system with dithering pulse-width-modulation controller
US8570107B2 (en) * 2011-04-01 2013-10-29 Mediatek Singapore Pte. Ltd. Clock generating apparatus and frequency calibrating method of the clock generating apparatus
US9515668B2 (en) * 2013-05-31 2016-12-06 The Regents Of The University Of Michigan Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement
JP5892116B2 (en) * 2013-07-17 2016-03-23 株式会社デンソー Excitation device
EP3202042B1 (en) * 2014-10-03 2023-12-06 Short Circuit Technologies LLC 60 ghz frequency generator incorporating third harmonic boost and extraction

Also Published As

Publication number Publication date
WO2014194308A1 (en) 2014-12-04
KR20160013945A (en) 2016-02-05
US9515668B2 (en) 2016-12-06
US20160118990A1 (en) 2016-04-28

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