SG11201505839UA - Map checkup apparatus, checkup method and checkup program - Google Patents
Map checkup apparatus, checkup method and checkup programInfo
- Publication number
- SG11201505839UA SG11201505839UA SG11201505839UA SG11201505839UA SG11201505839UA SG 11201505839U A SG11201505839U A SG 11201505839UA SG 11201505839U A SG11201505839U A SG 11201505839UA SG 11201505839U A SG11201505839U A SG 11201505839UA SG 11201505839U A SG11201505839U A SG 11201505839UA
- Authority
- SG
- Singapore
- Prior art keywords
- checkup
- map
- program
- checkup apparatus
- checkup method
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
- Image Processing (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2013/054543 WO2014128923A1 (en) | 2013-02-22 | 2013-02-22 | Map comparison apparatus, comparison method, and comparison program |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201505839UA true SG11201505839UA (en) | 2015-09-29 |
Family
ID=50396768
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201505839UA SG11201505839UA (en) | 2013-02-22 | 2013-02-22 | Map checkup apparatus, checkup method and checkup program |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5441286B1 (en) |
SG (1) | SG11201505839UA (en) |
TW (1) | TWI603077B (en) |
WO (1) | WO2014128923A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6716263B2 (en) | 2016-01-22 | 2020-07-01 | 株式会社ディスコ | Wafer processing method |
JP7284328B2 (en) * | 2018-09-19 | 2023-05-30 | ファスフォードテクノロジ株式会社 | Die bonding apparatus and semiconductor device manufacturing method |
JP7319070B2 (en) * | 2019-03-28 | 2023-08-01 | 東レエンジニアリング株式会社 | Mounting method and image display device manufacturing method |
CN111369505B (en) * | 2020-02-26 | 2024-04-30 | 广东省电信规划设计院有限公司 | Position correction method and device for chip components |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0722475A (en) * | 1993-06-29 | 1995-01-24 | Oki Electric Ind Co Ltd | Die bonding method and die bonder |
JP2001061069A (en) * | 1999-08-20 | 2001-03-06 | I4 Corp | Color balance adjustment method and system for digital image |
JP2002083784A (en) * | 2000-09-07 | 2002-03-22 | Sanyo Electric Co Ltd | Manufacturing method for semiconductor device |
JP2006013012A (en) * | 2004-06-24 | 2006-01-12 | Nidec Tosok Corp | Bonding device |
JP2009152450A (en) * | 2007-12-21 | 2009-07-09 | Renesas Technology Corp | Method of manufacturing semiconductor device |
JP2011061069A (en) * | 2009-09-11 | 2011-03-24 | Renesas Electronics Corp | Method for manufacturing semiconductor device |
-
2013
- 2013-02-22 JP JP2013548695A patent/JP5441286B1/en not_active Expired - Fee Related
- 2013-02-22 WO PCT/JP2013/054543 patent/WO2014128923A1/en active Application Filing
- 2013-02-22 SG SG11201505839UA patent/SG11201505839UA/en unknown
-
2014
- 2014-02-18 TW TW103105271A patent/TWI603077B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW201506387A (en) | 2015-02-16 |
JP5441286B1 (en) | 2014-03-12 |
WO2014128923A1 (en) | 2014-08-28 |
JPWO2014128923A1 (en) | 2017-02-02 |
TWI603077B (en) | 2017-10-21 |
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