SG10201809055VA - Semiconductor Package - Google Patents
Semiconductor PackageInfo
- Publication number
- SG10201809055VA SG10201809055VA SG10201809055VA SG10201809055VA SG10201809055VA SG 10201809055V A SG10201809055V A SG 10201809055VA SG 10201809055V A SG10201809055V A SG 10201809055VA SG 10201809055V A SG10201809055V A SG 10201809055VA SG 10201809055V A SG10201809055V A SG 10201809055VA
- Authority
- SG
- Singapore
- Prior art keywords
- passivation layer
- semiconductor chip
- connection pad
- chip
- chip substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 6
- 238000002161 passivation Methods 0.000 abstract 5
- 239000000758 substrate Substances 0.000 abstract 4
- 229910010272 inorganic material Inorganic materials 0.000 abstract 2
- 239000011147 inorganic material Substances 0.000 abstract 2
- 239000011368 organic material Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
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- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
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- H01—ELECTRIC ELEMENTS
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
OF THE DISCLOSURE A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer. FIG. 39
Applications Claiming Priority (1)
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KR1020180000532A KR20190083054A (en) | 2018-01-03 | 2018-01-03 | Semiconductor package |
Publications (1)
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SG10201809055VA true SG10201809055VA (en) | 2019-08-27 |
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SG10201809055VA SG10201809055VA (en) | 2018-01-03 | 2018-10-15 | Semiconductor Package |
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US (1) | US20190206841A1 (en) |
EP (1) | EP3509098A1 (en) |
KR (1) | KR20190083054A (en) |
CN (1) | CN109994443A (en) |
SG (1) | SG10201809055VA (en) |
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TWI697078B (en) * | 2018-08-03 | 2020-06-21 | 欣興電子股份有限公司 | Package substrate structure and method of bonding using the same |
WO2020133421A1 (en) * | 2018-12-29 | 2020-07-02 | 深南电路股份有限公司 | Diversified assembly printed circuit board and manufacturing method |
CN111095552B (en) * | 2019-08-15 | 2024-05-28 | 深圳市汇顶科技股份有限公司 | Chip interconnection structure, chip and chip interconnection method |
KR20210035546A (en) * | 2019-09-24 | 2021-04-01 | 삼성전자주식회사 | Semiconductor package |
KR20210042212A (en) * | 2019-10-08 | 2021-04-19 | 삼성전자주식회사 | Semiconductor package |
KR20220030676A (en) * | 2020-09-03 | 2022-03-11 | 삼성전자주식회사 | Semiconductor package |
US11610833B2 (en) | 2020-10-22 | 2023-03-21 | Nanya Technology Corporation | Conductive feature with non-uniform critical dimension and method of manufacturing the same |
KR20220065360A (en) * | 2020-11-13 | 2022-05-20 | 삼성전자주식회사 | Semiconductor package |
KR20220081036A (en) * | 2020-12-08 | 2022-06-15 | 삼성전자주식회사 | Semiconductor package and method of manufacturing the semiconductor package |
KR20220122155A (en) * | 2021-02-26 | 2022-09-02 | 삼성전자주식회사 | Semiconductor package including dummy chip |
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US5627106A (en) * | 1994-05-06 | 1997-05-06 | United Microelectronics Corporation | Trench method for three dimensional chip connecting during IC fabrication |
US6620731B1 (en) * | 1997-12-18 | 2003-09-16 | Micron Technology, Inc. | Method for fabricating semiconductor components and interconnects with contacts on opposing sides |
US6853076B2 (en) * | 2001-09-21 | 2005-02-08 | Intel Corporation | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same |
JP2003318178A (en) * | 2002-04-24 | 2003-11-07 | Seiko Epson Corp | Semiconductor device, its manufacturing method, circuit board, and electronic apparatus |
JP3646720B2 (en) * | 2003-06-19 | 2005-05-11 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus |
US8293636B2 (en) * | 2010-08-24 | 2012-10-23 | GlobalFoundries, Inc. | Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method |
KR20120091691A (en) * | 2011-02-09 | 2012-08-20 | 삼성전자주식회사 | Semiconductor device having warpage prevention adhesive pattern and fabricating method the same |
JP5870493B2 (en) * | 2011-02-24 | 2016-03-01 | セイコーエプソン株式会社 | Semiconductor devices, sensors and electronic devices |
JP2012256679A (en) * | 2011-06-08 | 2012-12-27 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
JP6232249B2 (en) * | 2013-02-27 | 2017-11-15 | 新光電気工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
KR102078848B1 (en) * | 2013-03-15 | 2020-02-18 | 삼성전자 주식회사 | Method of Fabricating Semiconductor Stack Structures |
US9466581B2 (en) * | 2013-10-18 | 2016-10-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package device and manufacturing method thereof |
US9570421B2 (en) * | 2013-11-14 | 2017-02-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure |
JP2015162660A (en) * | 2014-02-28 | 2015-09-07 | イビデン株式会社 | Printed wiring board, manufacturing method of the same, and package-on-package |
KR102206113B1 (en) * | 2014-03-28 | 2021-01-25 | 에스케이하이닉스 주식회사 | Semiconductor device having through silicon via, semiconductor packages including the same and the method for manufacturing semiconductor device |
JP6276151B2 (en) * | 2014-09-17 | 2018-02-07 | 東芝メモリ株式会社 | Semiconductor device |
JP6489965B2 (en) * | 2015-07-14 | 2019-03-27 | 新光電気工業株式会社 | Electronic component device and manufacturing method thereof |
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2018
- 2018-01-03 KR KR1020180000532A patent/KR20190083054A/en not_active Application Discontinuation
- 2018-08-21 US US16/106,521 patent/US20190206841A1/en not_active Abandoned
- 2018-09-26 EP EP18196815.7A patent/EP3509098A1/en not_active Withdrawn
- 2018-10-15 SG SG10201809055VA patent/SG10201809055VA/en unknown
- 2018-11-27 CN CN201811425214.8A patent/CN109994443A/en active Pending
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EP3509098A1 (en) | 2019-07-10 |
KR20190083054A (en) | 2019-07-11 |
US20190206841A1 (en) | 2019-07-04 |
CN109994443A (en) | 2019-07-09 |
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