SG10201808209UA - Stacked memory device, a system including the same and an associated method - Google Patents

Stacked memory device, a system including the same and an associated method

Info

Publication number
SG10201808209UA
SG10201808209UA SG10201808209UA SG10201808209UA SG10201808209UA SG 10201808209U A SG10201808209U A SG 10201808209UA SG 10201808209U A SG10201808209U A SG 10201808209UA SG 10201808209U A SG10201808209U A SG 10201808209UA SG 10201808209U A SG10201808209U A SG 10201808209UA
Authority
SG
Singapore
Prior art keywords
calculation
memory
semiconductor dies
memory device
semiconductor die
Prior art date
Application number
SG10201808209UA
Inventor
Shin Hyun-Sung
Choi Ik-Joon
Kim So-Young
Byun Tae-Kyu
YOUN Jae-Youn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201808209UA publication Critical patent/SG10201808209UA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2272—Latency related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Memory System (AREA)

Abstract

A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation 5 unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is 10 respectively read from the memory integrated circuits of the calculation semiconductor dies. FIG. 1 15
SG10201808209UA 2017-09-27 2018-09-20 Stacked memory device, a system including the same and an associated method SG10201808209UA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020170125481A KR102395463B1 (en) 2017-09-27 2017-09-27 Stacked memory device, system including the same and associated method

Publications (1)

Publication Number Publication Date
SG10201808209UA true SG10201808209UA (en) 2019-04-29

Family

ID=65638267

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201808209UA SG10201808209UA (en) 2017-09-27 2018-09-20 Stacked memory device, a system including the same and an associated method

Country Status (7)

Country Link
US (3) US10553260B2 (en)
JP (1) JP7317478B2 (en)
KR (1) KR102395463B1 (en)
CN (1) CN109560078B (en)
DE (1) DE102018108702A1 (en)
SG (1) SG10201808209UA (en)
TW (1) TWI750365B (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102395463B1 (en) 2017-09-27 2022-05-09 삼성전자주식회사 Stacked memory device, system including the same and associated method
KR20200066953A (en) 2018-12-03 2020-06-11 삼성전자주식회사 Semiconductor memory device employing processing in memory (PIM) and operating method for the same
US11094371B2 (en) 2019-03-11 2021-08-17 Samsung Electronics Co., Ltd. Memory device for processing operation and method of operating the same
US11171115B2 (en) 2019-03-18 2021-11-09 Kepler Computing Inc. Artificial intelligence processor with three-dimensional stacked memory
US11836102B1 (en) 2019-03-20 2023-12-05 Kepler Computing Inc. Low latency and high bandwidth artificial intelligence processor
CN111952298B (en) * 2019-05-17 2023-12-29 芯盟科技有限公司 Neural network intelligent chip and forming method thereof
US11152343B1 (en) 2019-05-31 2021-10-19 Kepler Computing, Inc. 3D integrated ultra high-bandwidth multi-stacked memory
US11844223B1 (en) 2019-05-31 2023-12-12 Kepler Computing Inc. Ferroelectric memory chiplet as unified memory in a multi-dimensional packaging
CN113906505B (en) * 2019-05-31 2023-04-18 美光科技公司 Memory assembly for system-on-chip devices
WO2021030750A1 (en) 2019-08-14 2021-02-18 Supermem, Inc. Computing memory systems
CN110942793B (en) * 2019-10-23 2021-11-23 北京新忆科技有限公司 Memory device
KR20210081663A (en) 2019-12-24 2021-07-02 삼성전자주식회사 Interconnect device, operation method of interconnect device, and artificial intelligence(ai) accelerator system
US20210350837A1 (en) * 2020-01-07 2021-11-11 SK Hynix Inc. Processing-in-memory (pim) device
US11842266B2 (en) * 2020-01-07 2023-12-12 SK Hynix Inc. Processing-in-memory (PIM) device, controller for controlling the PIM device, and PIM system including the PIM device and the controller
US11537323B2 (en) * 2020-01-07 2022-12-27 SK Hynix Inc. Processing-in-memory (PIM) device
KR20210093521A (en) 2020-01-20 2021-07-28 삼성전자주식회사 High bandwidth memory and system having the same
KR20210098728A (en) * 2020-02-03 2021-08-11 삼성전자주식회사 Stacked memory device, and operating method thereof
US11189347B2 (en) * 2020-03-13 2021-11-30 Micron Technology, Inc. Resource management for memory die-specific operations
US20230153587A1 (en) * 2020-03-30 2023-05-18 Rambus Inc. Stacked-Die Neural Network with Integrated High-Bandwidth Memory
WO2021198841A1 (en) * 2020-04-03 2021-10-07 株式会社半導体エネルギー研究所 Semiconductor device
CN113704137A (en) * 2020-07-30 2021-11-26 西安紫光国芯半导体有限公司 In-memory computing module and method, in-memory computing network and construction method
KR20220030106A (en) 2020-09-02 2022-03-10 삼성전자주식회사 Storage device, method for operating the same and electronic device including the same
KR20220031793A (en) 2020-09-03 2022-03-14 삼성전자주식회사 Memory device, memory system having the same, controller for controlling the same, and operating methed thereof
KR20220032366A (en) 2020-09-07 2022-03-15 삼성전자주식회사 Memory device performing configurable mode set and Operating method thereof
TWI792665B (en) * 2021-01-21 2023-02-11 創惟科技股份有限公司 Ai algorithm operation accelerator and method thereof, computing system and non-transitory computer readable media
JPWO2022238798A1 (en) * 2021-05-10 2022-11-17
US11791233B1 (en) 2021-08-06 2023-10-17 Kepler Computing Inc. Ferroelectric or paraelectric memory and logic chiplet with thermal management in a multi-dimensional packaging
US20230051863A1 (en) * 2021-08-10 2023-02-16 Micron Technology, Inc. Memory device for wafer-on-wafer formed memory and logic
US11893240B2 (en) 2021-10-28 2024-02-06 Qualcomm Incorporated Reducing latency in pseudo channel based memory systems
WO2024028680A1 (en) * 2022-08-02 2024-02-08 株式会社半導体エネルギー研究所 Semiconductor device

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5159572A (en) 1974-11-20 1976-05-24 Matsushita Electric Ind Co Ltd KUTSUKINGUTEEBURUNADONO CHORIKI
JPS60262253A (en) * 1984-06-07 1985-12-25 Agency Of Ind Science & Technol Memory data processing circuit
EP0446721B1 (en) 1990-03-16 2000-12-20 Texas Instruments Incorporated Distributed processing memory
US5528549A (en) * 1993-05-28 1996-06-18 Texas Instruments Incorporated Apparatus, systems and methods for distributed signal processing
JP3189727B2 (en) * 1997-04-15 2001-07-16 日本電気株式会社 Packet-type memory LSI with built-in coprocessor, memory system using the same, and control method therefor
WO2003088033A1 (en) 2002-04-09 2003-10-23 University Of Rochester Multiplier-based processor-in-memory architectures for image and graphics processing
JP4309368B2 (en) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 Semiconductor memory device
JP4423453B2 (en) 2005-05-25 2010-03-03 エルピーダメモリ株式会社 Semiconductor memory device
JP4799157B2 (en) 2005-12-06 2011-10-26 エルピーダメモリ株式会社 Multilayer semiconductor device
JP2008140220A (en) * 2006-12-04 2008-06-19 Nec Corp Semiconductor device
JP5331427B2 (en) 2008-09-29 2013-10-30 株式会社日立製作所 Semiconductor device
US8127185B2 (en) * 2009-01-23 2012-02-28 Micron Technology, Inc. Memory devices and methods for managing error regions
US8234460B2 (en) 2009-06-04 2012-07-31 Micron Technology, Inc. Communication between internal and external processors
US9477636B2 (en) 2009-10-21 2016-10-25 Micron Technology, Inc. Memory having internal processors and data communication methods in memory
US8719516B2 (en) 2009-10-21 2014-05-06 Micron Technology, Inc. Memory having internal processors and methods of controlling memory access
US8612809B2 (en) 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
US8437163B2 (en) * 2010-02-11 2013-05-07 Micron Technology, Inc. Memory dies, stacked memories, memory devices and methods
KR101667656B1 (en) 2010-03-24 2016-10-20 삼성전자주식회사 Method of forming package on package
US9804996B2 (en) 2012-12-21 2017-10-31 Advanced Micro Devices, Inc. Computation memory operations in a logic layer of a stacked memory
WO2014145150A1 (en) 2013-03-15 2014-09-18 Beats Electronics, Llc Memory management techniques for block-based convolution
US8971124B1 (en) 2013-08-08 2015-03-03 Micron Technology, Inc. Apparatuses and methods for performing logical operations using sensing circuitry
US9019785B2 (en) 2013-09-19 2015-04-28 Micron Technology, Inc. Data shifting via a number of isolation devices
JP6680454B2 (en) * 2014-03-17 2020-04-15 国立研究開発法人産業技術総合研究所 LSI chip stacking system
JP6637906B2 (en) * 2014-05-08 2020-01-29 マイクロン テクノロジー，インク． Hybrid Memory Cube System Interconnection Directory Based Cache Coherence Method
KR102246878B1 (en) * 2014-05-29 2021-04-30 삼성전자 주식회사 A semiconductor memory device, a memory module including the same, and a memory system including the same
US9514093B2 (en) 2014-09-26 2016-12-06 Intel Corporation Method and apparatus for stacking core and uncore dies having landing slots
US9411726B2 (en) 2014-09-30 2016-08-09 Samsung Electronics Co., Ltd. Low power computation architecture
US9836277B2 (en) * 2014-10-01 2017-12-05 Samsung Electronics Co., Ltd. In-memory popcount support for real time analytics
US9880752B2 (en) * 2015-09-28 2018-01-30 Western Digital Technologies, Inc. Memory die temperature adjustment based on a power condition
CN106782666B (en) * 2015-11-25 2020-05-05 北京大学深圳研究生院 Three-dimensional stacked memory
JP2017123208A (en) 2016-01-06 2017-07-13 ルネサスエレクトロニクス株式会社 Semiconductor storage device
US11079936B2 (en) 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
US9997232B2 (en) * 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
KR101838379B1 (en) 2016-05-04 2018-03-13 연세대학교 산학협력단 Composition for increasing salivary secretion, or prevention, improvement or treatment of xerostomia of disorder of salivation comprising curcuma xanthorrhiza extract or xanthorrhizol
KR102395463B1 (en) 2017-09-27 2022-05-09 삼성전자주식회사 Stacked memory device, system including the same and associated method

Also Published As

Publication number Publication date
JP2019061677A (en) 2019-04-18
KR102395463B1 (en) 2022-05-09
KR20190036358A (en) 2019-04-04
US20190096453A1 (en) 2019-03-28
JP7317478B2 (en) 2023-07-31
US11114139B2 (en) 2021-09-07
US20200152244A1 (en) 2020-05-14
CN109560078A (en) 2019-04-02
US10923165B2 (en) 2021-02-16
DE102018108702A1 (en) 2019-03-28
US10553260B2 (en) 2020-02-04
CN109560078B (en) 2023-10-03
TWI750365B (en) 2021-12-21
US20210166740A1 (en) 2021-06-03
TW201915730A (en) 2019-04-16

Similar Documents

Publication Publication Date Title
SG10201808209UA (en) Stacked memory device, a system including the same and an associated method
SG10201808497WA (en) Stacked semiconductor die assemblies with partitioned logic and associated systems and methods
EP4254214A3 (en) Integration of a programmable device and a processing system in an integrated circuit package
WO2019089816A3 (en) System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
TW201612755A (en) Hybrid memory cube system interconnect directory-based cache coherence methodology
MY193320A (en) Integrated circuit die having backside passive components and methods associated therewith
GB2554627A (en) Modular array of vertically integrated superconducting qubit devices for scalable quantum computing
TW201612753A (en) In-memory lightweight coherency
EP4321993A3 (en) Programmable matrix processing engine
GB2560480A (en) Three-dimensional integration of neurosynaptic chips
WO2014051741A3 (en) Integrated circuits having accessible and inaccessible physically unclonable functions
SG10201806114YA (en) Semiconductor memory devices
EA201791413A1 (en) PLACEMENT OF THE MEMORY CONTROLLER IN A THREE-DIMENSIONAL (3D) INTEGRAL SCHEME (IC) (3DIC) USING THE DISTRIBUTED MASSIFUS OF TRANSITIONAL HOLES IN SILICON (TSV)
IN2014MN02115A (en)
WO2017169879A3 (en) Solid-state imaging element, imaging device, and electronic device
KR20220162672A (en) Latch circuit and semiconductor apparatus including the same
EP3629374A3 (en) Stacked-substrate dram semiconductor devices
JP2014143680A5 (en)
WO2015127207A4 (en) Method and apparatus for incorporating passive devices in an integrated passive device separate from a die
TW201614741A (en) Method of manufacturing semiconductor device
JP2015156640A5 (en) Information processing device
MX2016013380A (en) Load panel system.
IN2014DE00712A (en)
WO2017184300A3 (en) V1 and higher layers programmable eco standard cells
SG10201901508YA (en) High bandwidth memory device and system device having the same