SG10201802515PA - Packaging process - Google Patents

Packaging process

Info

Publication number
SG10201802515PA
SG10201802515PA SG10201802515PA SG10201802515PA SG 10201802515P A SG10201802515P A SG 10201802515PA SG 10201802515P A SG10201802515P A SG 10201802515PA SG 10201802515P A SG10201802515P A SG 10201802515PA
Authority
SG
Singapore
Prior art keywords
packaging process
electronic component
packaging
consequently
thickness
Prior art date
Application number
Inventor
Beng Beng Lim
Original Assignee
Delta Electronics Int’L Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delta Electronics Int’L Singapore Pte Ltd filed Critical Delta Electronics Int’L Singapore Pte Ltd
Priority to SG10201802515P priority Critical patent/SG10201802515PA/en
Priority to US15/955,085 priority patent/US10424573B1/en
Priority to EP18171076.5A priority patent/EP3547353B1/en
Priority to CN201810469635.4A priority patent/CN110310928B/en
Publication of SG10201802515PA publication Critical patent/SG10201802515PA/en

Links

Classifications

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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L2224/24265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
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    • H01L2224/82909—Post-treatment of the connector or the bonding area
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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    • H01L2924/14—Integrated circuits
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Transducers For Ultrasonic Waves (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PACKAGINGPROCESS OF THE DISCLOSURE A packaging process of an electronic component is provided. By the packaging process of the disclosure, the electronic component is grinded by the back grinding process. Consequently, thickness of the electronic component may be reduced to less than or equal to // m. The packaging process may achieve ultra-thin thickness and reduce the space of the power module. Moreover, the packaging process forms the contact pads with drilling process and grinding process without photolithography process. Consequently, the packaging process is advantageous because of lower cost and uniform thickness of the contact pads. Fig. 10 19
SG10201802515P 2018-03-27 2018-03-27 Packaging process SG10201802515PA (en)

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EP18171076.5A EP3547353B1 (en) 2018-03-27 2018-05-07 Packaging process
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EP3557608A1 (en) * 2018-04-19 2019-10-23 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Packaged integrated circuit with interposing functionality and method for manufacturing such a packaged integrated circuit
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
US20210375672A1 (en) * 2020-05-27 2021-12-02 Taiwan Semiconductor Manfacturing Co., Ltd. Redistribution Lines Having Nano Columns and Method Forming Same
CN113363160A (en) * 2020-05-27 2021-09-07 台湾积体电路制造股份有限公司 Semiconductor device and method of forming the same

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JP4592891B2 (en) * 1999-11-26 2010-12-08 イビデン株式会社 Multilayer circuit board and semiconductor device
FI119215B (en) 2002-01-31 2008-08-29 Imbera Electronics Oy A method for immersing a component in a substrate and an electronic module
US6974724B2 (en) 2004-04-28 2005-12-13 Nokia Corporation Shielded laminated structure with embedded chips
CN101369617B (en) * 2007-08-13 2011-01-12 佰鸿工业股份有限公司 LED device with high cooling property
US20100133682A1 (en) 2008-12-02 2010-06-03 Infineon Technologies Ag Semiconductor device
US20100212946A1 (en) * 2009-02-20 2010-08-26 Ibiden Co., Ltd Wiring board and method for manufacturing the same
US20100264566A1 (en) * 2009-03-17 2010-10-21 Suss Microtec Inc Rapid fabrication of a microelectronic temporary support for inorganic substrates
US20110084372A1 (en) 2009-10-14 2011-04-14 Advanced Semiconductor Engineering, Inc. Package carrier, semiconductor package, and process for fabricating same
US9177926B2 (en) * 2011-12-30 2015-11-03 Deca Technologies Inc Semiconductor device and method comprising thickened redistribution layers
US8357564B2 (en) 2010-05-17 2013-01-22 Stats Chippac, Ltd. Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die
US8916481B2 (en) * 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US9559039B2 (en) 2012-09-17 2017-01-31 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
SG10201400390YA (en) * 2014-03-05 2015-10-29 Delta Electronics Int L Singapore Pte Ltd Package structure
US9269699B2 (en) 2014-05-09 2016-02-23 Alpha And Omega Semiconductor Incorporated Embedded package and method thereof
DE102015104956A1 (en) 2015-03-31 2016-10-06 Infineon Technologies Ag Printed circuit board with a lead frame with inserted packaged semiconductor chips
KR101681031B1 (en) 2015-11-17 2016-12-01 주식회사 네패스 Semiconductor package and method of manufacturing the same
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