SG10201700013VA - Semiconductor memory device and method for manufacturing same - Google Patents
Semiconductor memory device and method for manufacturing sameInfo
- Publication number
- SG10201700013VA SG10201700013VA SG10201700013VA SG10201700013VA SG10201700013VA SG 10201700013V A SG10201700013V A SG 10201700013VA SG 10201700013V A SG10201700013V A SG 10201700013VA SG 10201700013V A SG10201700013V A SG 10201700013VA SG 10201700013V A SG10201700013V A SG 10201700013VA
- Authority
- SG
- Singapore
- Prior art keywords
- memory device
- semiconductor memory
- manufacturing same
- manufacturing
- same
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Geometry (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662327157P | 2016-04-25 | 2016-04-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201700013VA true SG10201700013VA (en) | 2017-11-29 |
Family
ID=60090395
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201700013VA SG10201700013VA (en) | 2016-04-25 | 2017-01-03 | Semiconductor memory device and method for manufacturing same |
Country Status (4)
Country | Link |
---|---|
US (1) | US9929177B2 (en) |
CN (1) | CN107305894B (en) |
SG (1) | SG10201700013VA (en) |
TW (1) | TWI624007B (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10734402B2 (en) * | 2017-09-07 | 2020-08-04 | Toshiba Memory Corporation | Semiconductor device and method of fabricating the same |
US10886293B2 (en) | 2017-09-07 | 2021-01-05 | Toshiba Memory Corporation | Semiconductor device and method of fabricating the same |
US10892274B2 (en) | 2017-11-09 | 2021-01-12 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and fabricating methods thereof |
CN109887913B (en) * | 2017-11-09 | 2021-02-23 | 长江存储科技有限责任公司 | NAND string structure and preparation method thereof |
JP2019201074A (en) * | 2018-05-15 | 2019-11-21 | 東芝メモリ株式会社 | Semiconductor storage |
JP2020126938A (en) * | 2019-02-05 | 2020-08-20 | キオクシア株式会社 | Semiconductor storage device |
JP2020150199A (en) * | 2019-03-15 | 2020-09-17 | キオクシア株式会社 | Semiconductor storage device |
JP2020155494A (en) * | 2019-03-18 | 2020-09-24 | キオクシア株式会社 | Semiconductor storage |
JP2020155714A (en) * | 2019-03-22 | 2020-09-24 | キオクシア株式会社 | Semiconductor storage device |
US10770476B1 (en) | 2019-04-01 | 2020-09-08 | Macronix International Co., Ltd. | Semiconductor structure for three-dimensional memory device and manufacturing method thereof |
TWI701816B (en) * | 2019-04-01 | 2020-08-11 | 旺宏電子股份有限公司 | Semiconductor structure for three-dimensional memory device and manufacturing method thereof |
TWI738202B (en) * | 2019-06-03 | 2021-09-01 | 旺宏電子股份有限公司 | 3d flash memory and array layout thereof |
JP2021048228A (en) | 2019-09-18 | 2021-03-25 | キオクシア株式会社 | Memory device |
CN113192968A (en) * | 2020-05-27 | 2021-07-30 | 长江存储科技有限责任公司 | Three-dimensional memory device |
WO2022099621A1 (en) * | 2020-11-13 | 2022-05-19 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
JP2023045239A (en) * | 2021-09-21 | 2023-04-03 | キオクシア株式会社 | semiconductor storage device |
JP2024510229A (en) * | 2021-10-30 | 2024-03-06 | 長江存儲科技有限責任公司 | Method for forming semiconductor devices |
WO2023070619A1 (en) * | 2021-10-30 | 2023-05-04 | Yangtze Memory Technologies Co., Ltd. | Semiconductor memory device and method for forming the same |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100314678A1 (en) | 2009-06-12 | 2010-12-16 | Se-Yun Lim | Non-volatile memory device and method for fabricating the same |
KR101549690B1 (en) * | 2009-12-18 | 2015-09-14 | 삼성전자주식회사 | 3 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same |
US8482051B2 (en) | 2010-01-11 | 2013-07-09 | Hynix Semiconductor Inc. | 3D nonvolatile memory device including a plurality of channel contacts coupled to a plurality of channel layers and a plurality of section lines coupled to the plurality of channel contacts and method for fabricating the same |
KR101763420B1 (en) | 2010-09-16 | 2017-08-01 | 삼성전자주식회사 | Therr dimensional semiconductor memory devices and methods of fabricating the same |
KR101113765B1 (en) | 2010-12-31 | 2012-02-27 | 주식회사 하이닉스반도체 | Nonvolatile memory device and method for fabricating the same |
KR101842900B1 (en) * | 2011-02-16 | 2018-03-29 | 삼성전자주식회사 | three dimensional semiconductor memory device and method for manufacturing the same |
US8692313B2 (en) * | 2011-04-29 | 2014-04-08 | SK Hynix Inc. | Non-volatile memory device and method for fabricating the same |
KR20140076799A (en) | 2012-12-13 | 2014-06-23 | 에스케이하이닉스 주식회사 | Semiconductor device and method of manufacturing the same |
US9281345B2 (en) * | 2013-07-09 | 2016-03-08 | Kabushiki Kaisha Toshiba | Resistance change type memory device with three-dimensional structure |
KR20150020423A (en) | 2013-08-14 | 2015-02-26 | 에스케이하이닉스 주식회사 | Semiconductor device |
JP2017010951A (en) * | 2014-01-10 | 2017-01-12 | 株式会社東芝 | Semiconductor memory and its manufacturing method |
JP2015133458A (en) * | 2014-01-16 | 2015-07-23 | 株式会社東芝 | Nonvolatile semiconductor storage device |
KR102161781B1 (en) | 2014-02-03 | 2020-10-05 | 삼성전자주식회사 | Vertical memory devices |
US11018149B2 (en) * | 2014-03-27 | 2021-05-25 | Intel Corporation | Building stacked hollow channels for a three dimensional circuit device |
US9847340B2 (en) | 2014-03-27 | 2017-12-19 | Intel Corporation | Methods of tunnel oxide layer formation in 3D NAND memory structures and associated devices |
KR102323571B1 (en) * | 2014-07-01 | 2021-11-09 | 삼성전자주식회사 | Semiconductor device and method of manufacturing the same |
KR20160011095A (en) * | 2014-07-21 | 2016-01-29 | 에스케이하이닉스 주식회사 | Three dimensional non-volatile memory device |
KR20160080365A (en) * | 2014-12-29 | 2016-07-08 | 에스케이하이닉스 주식회사 | Electronic device and manufacturing method thereof |
US9793139B2 (en) * | 2015-10-29 | 2017-10-17 | Sandisk Technologies Llc | Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines |
-
2016
- 2016-12-15 TW TW105141543A patent/TWI624007B/en active
-
2017
- 2017-01-03 SG SG10201700013VA patent/SG10201700013VA/en unknown
- 2017-01-12 US US15/404,420 patent/US9929177B2/en active Active
- 2017-01-13 CN CN201710024411.8A patent/CN107305894B/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN107305894B (en) | 2021-05-07 |
TW201739007A (en) | 2017-11-01 |
TWI624007B (en) | 2018-05-11 |
US20170309638A1 (en) | 2017-10-26 |
CN107305894A (en) | 2017-10-31 |
US9929177B2 (en) | 2018-03-27 |
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