SG10201600224SA - Dedicated ssr pipeline stage of router for express traversal (extra) noc - Google Patents

Dedicated ssr pipeline stage of router for express traversal (extra) noc

Info

Publication number
SG10201600224SA
SG10201600224SA SG10201600224SA SG10201600224SA SG10201600224SA SG 10201600224S A SG10201600224S A SG 10201600224SA SG 10201600224S A SG10201600224S A SG 10201600224SA SG 10201600224S A SG10201600224S A SG 10201600224SA SG 10201600224S A SG10201600224S A SG 10201600224SA
Authority
SG
Singapore
Prior art keywords
noc
ssr
traversal
router
express
Prior art date
Application number
SG10201600224SA
Inventor
Zhiguo Ge
Naxin Zhang
Original Assignee
Huawei Int Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Int Pte Ltd filed Critical Huawei Int Pte Ltd
Priority to SG10201600224SA priority Critical patent/SG10201600224SA/en
Priority to PCT/SG2017/050003 priority patent/WO2017123154A1/en
Priority to CN201780005891.1A priority patent/CN108431790B/en
Publication of SG10201600224SA publication Critical patent/SG10201600224SA/en
Priority to US16/032,804 priority patent/US10554584B2/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4247—Bus transfer protocol, e.g. handshake; Synchronisation on a daisy chain bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1515—Non-blocking multistage, e.g. Clos
    • H04L49/1546—Non-blocking multistage, e.g. Clos using pipelined operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H04L49/1553—Interconnection of ATM switching modules, e.g. ATM switching fabrics
    • H04L49/1576—Crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9005—Buffering arrangements using dynamic buffer space allocation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
SG10201600224SA 2016-01-12 2016-01-12 Dedicated ssr pipeline stage of router for express traversal (extra) noc SG10201600224SA (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
SG10201600224SA SG10201600224SA (en) 2016-01-12 2016-01-12 Dedicated ssr pipeline stage of router for express traversal (extra) noc
PCT/SG2017/050003 WO2017123154A1 (en) 2016-01-12 2017-01-04 Dedicated ssr pipeline stage of router for express traversal (extra) noc
CN201780005891.1A CN108431790B (en) 2016-01-12 2017-01-04 Special SSR pipeline stage for routers of high-speed migration (EXTRA) NoC
US16/032,804 US10554584B2 (en) 2016-01-12 2018-07-11 Dedicated SSR pipeline stage of router for express traversal (EXTRA) NoC

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201600224SA SG10201600224SA (en) 2016-01-12 2016-01-12 Dedicated ssr pipeline stage of router for express traversal (extra) noc

Publications (1)

Publication Number Publication Date
SG10201600224SA true SG10201600224SA (en) 2017-08-30

Family

ID=57868313

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201600224SA SG10201600224SA (en) 2016-01-12 2016-01-12 Dedicated ssr pipeline stage of router for express traversal (extra) noc

Country Status (4)

Country Link
US (1) US10554584B2 (en)
CN (1) CN108431790B (en)
SG (1) SG10201600224SA (en)
WO (1) WO2017123154A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11496418B1 (en) * 2020-08-25 2022-11-08 Xilinx, Inc. Packet-based and time-multiplexed network-on-chip
KR20220102160A (en) 2021-01-11 2022-07-20 삼성전자주식회사 Switch for transmitting packet, network on chip having the same, and operating method thereof
CN113114593B (en) * 2021-04-12 2022-03-15 合肥工业大学 Dual-channel router in network on chip and routing method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838684A (en) * 1996-02-22 1998-11-17 Fujitsu, Ltd. Low latency, high clock frequency plesioasynchronous packet-based crossbar switching chip system and method
US8028299B2 (en) * 2005-04-21 2011-09-27 Waratek Pty, Ltd. Computer architecture and method of operation for multi-computer distributed processing with finalization of objects
US8095774B1 (en) * 2007-07-05 2012-01-10 Silver Peak Systems, Inc. Pre-fetching data into a memory
US8385194B2 (en) * 2007-03-13 2013-02-26 Alcatel Lucent Quality of service admission control network
US7657693B2 (en) * 2007-09-28 2010-02-02 Intel Corporation Router to use three levels of arbitration for a crossbar channel
TWI384814B (en) * 2009-02-06 2013-02-01 Univ Nat Taiwan Differential radio frequency signal transmitter and receiver and wireless radio frequency signal transceiver system
US8509078B2 (en) * 2009-02-12 2013-08-13 Microsoft Corporation Bufferless routing in on-chip interconnection networks
CN101841420B (en) * 2010-05-24 2011-11-23 中国人民解放军国防科学技术大学 Network-on-chip oriented low delay router structure
US9015448B2 (en) * 2010-06-17 2015-04-21 Advanced Micro Devices, Inc. Message broadcast with router bypassing
JP5200197B2 (en) * 2011-03-28 2013-05-15 パナソニック株式会社 Repeater, repeater control method, and program
US8711867B2 (en) * 2011-08-26 2014-04-29 Sonics, Inc. Credit flow control scheme in a router with flexible link widths utilizing minimal storage
FR2985825B1 (en) * 2012-01-13 2014-12-05 Commissariat Energie Atomique SYSTEM AND METHOD FOR CORRESPONDENCE MANAGEMENT BETWEEN A CACHE MEMORY AND A MAIN MEMORY
CN102629913B (en) * 2012-04-11 2014-12-24 浙江大学 Router device suitable for globally asynchronous locally synchronous on-chip network
US20140092740A1 (en) * 2012-09-29 2014-04-03 Ren Wang Adaptive packet deflection to achieve fair, low-cost, and/or energy-efficient quality of service in network on chip devices
US8885510B2 (en) * 2012-10-09 2014-11-11 Netspeed Systems Heterogeneous channel capacities in an interconnect
US9250679B2 (en) * 2013-03-08 2016-02-02 Intel Corporation Reduced wake up delay for on-die routers
US9661080B2 (en) * 2014-10-21 2017-05-23 Helium Systems, Inc. Systems and methods for smart device networking with an endpoint and a bridge
US10116577B2 (en) * 2014-12-04 2018-10-30 Dell Products Lp Detecting path MTU mismatch at first-hop router
US10356209B2 (en) * 2015-11-30 2019-07-16 Futurewei Technologies, Inc. System and method to support context-aware content requests in information centric networks

Also Published As

Publication number Publication date
CN108431790A (en) 2018-08-21
WO2017123154A1 (en) 2017-07-20
CN108431790B (en) 2022-01-11
US10554584B2 (en) 2020-02-04
US20180324110A1 (en) 2018-11-08

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