SE9803204L - Method and apparatus for buried electronics components - Google Patents
Method and apparatus for buried electronics componentsInfo
- Publication number
- SE9803204L SE9803204L SE9803204A SE9803204A SE9803204L SE 9803204 L SE9803204 L SE 9803204L SE 9803204 A SE9803204 A SE 9803204A SE 9803204 A SE9803204 A SE 9803204A SE 9803204 L SE9803204 L SE 9803204L
- Authority
- SE
- Sweden
- Prior art keywords
- carrier
- main surface
- connecting means
- dielectric layer
- arranging
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/01005—Boron [B]
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- H01L2924/01006—Carbon [C]
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- H01L2924/01029—Copper [Cu]
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01039—Yttrium [Y]
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- H01L2924/01087—Francium [Fr]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
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- H01L2924/30105—Capacitance
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- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
A method for arranging one or more electronic components (100) on a carrier (200). The electronic components have a number of contact points (110) arranged on a first surface (120). The carrier has a second main surface (210) and a third main surface (220). In the carrier there are also arranged one or more first apertures (230) with a depth extending from the second main surface towards the third main surface. The method comprises the stages: arranging of connecting means (130) on the contact points, where the connecting means have a first end (140) connected to one of the contact points and a second end (150) at a distance from the contact point, arranging of the electronic components in the apertures in the carrier so that the connecting means are pointed away from the third main surface of the carrier, application of a dielectric layer (300) on the second main surface of the carrier, where the dielectric layer also covers the electronic component, exposure of the second end of the connecting means in the dielectric layer, and connection of the second end of the connecting means to circuit paths (310) arranged on the free surface of the dielectric layer.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803204A SE514529C2 (en) | 1998-09-21 | 1998-09-21 | Method and apparatus for buried electronics components |
EP99951342A EP1116268A2 (en) | 1998-09-21 | 1999-09-21 | Method and device for buried chips |
AU63799/99A AU6379999A (en) | 1998-09-21 | 1999-09-21 | Method and device for buried chips |
PCT/SE1999/001643 WO2000017924A2 (en) | 1998-09-21 | 1999-09-21 | Method and device for buried chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803204A SE514529C2 (en) | 1998-09-21 | 1998-09-21 | Method and apparatus for buried electronics components |
Publications (3)
Publication Number | Publication Date |
---|---|
SE9803204D0 SE9803204D0 (en) | 1998-09-21 |
SE9803204L true SE9803204L (en) | 2000-03-22 |
SE514529C2 SE514529C2 (en) | 2001-03-05 |
Family
ID=20412669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE9803204A SE514529C2 (en) | 1998-09-21 | 1998-09-21 | Method and apparatus for buried electronics components |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1116268A2 (en) |
AU (1) | AU6379999A (en) |
SE (1) | SE514529C2 (en) |
WO (1) | WO2000017924A2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SE515856C2 (en) | 1999-05-19 | 2001-10-22 | Ericsson Telefon Ab L M | Carrier for electronic components |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS577147A (en) * | 1980-06-17 | 1982-01-14 | Citizen Watch Co Ltd | Mounting construction of semiconductor device |
US5745984A (en) * | 1995-07-10 | 1998-05-05 | Martin Marietta Corporation | Method for making an electronic module |
JP2842378B2 (en) * | 1996-05-31 | 1999-01-06 | 日本電気株式会社 | High-density mounting structure for electronic circuit boards |
-
1998
- 1998-09-21 SE SE9803204A patent/SE514529C2/en not_active IP Right Cessation
-
1999
- 1999-09-21 EP EP99951342A patent/EP1116268A2/en not_active Withdrawn
- 1999-09-21 WO PCT/SE1999/001643 patent/WO2000017924A2/en active Application Filing
- 1999-09-21 AU AU63799/99A patent/AU6379999A/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2000017924A2 (en) | 2000-03-30 |
SE9803204D0 (en) | 1998-09-21 |
SE514529C2 (en) | 2001-03-05 |
WO2000017924A3 (en) | 2000-08-17 |
AU6379999A (en) | 2000-04-10 |
EP1116268A2 (en) | 2001-07-18 |
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Legal Events
Date | Code | Title | Description |
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NUG | Patent has lapsed |