SE8103279L - SAMPLING AND HALLAR CIRCUITS WITH OFFSET ELIMINATION - Google Patents
SAMPLING AND HALLAR CIRCUITS WITH OFFSET ELIMINATIONInfo
- Publication number
- SE8103279L SE8103279L SE8103279A SE8103279A SE8103279L SE 8103279 L SE8103279 L SE 8103279L SE 8103279 A SE8103279 A SE 8103279A SE 8103279 A SE8103279 A SE 8103279A SE 8103279 L SE8103279 L SE 8103279L
- Authority
- SE
- Sweden
- Prior art keywords
- operational amplifier
- transistor
- transistors
- capacitor
- input lead
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
Landscapes
- Amplifiers (AREA)
- Filters That Use Time-Delay Elements (AREA)
- Measurement Of Current Or Voltage (AREA)
Abstract
An operational amplifier based sample and hold circuit adapted for implementation as an integrated circuit is comprised of MOS transistor elements. The operational amplifier (11) has a positive terminal (+) connected to ground and a negative input lead connected to one side of a capacitor (20), the other side of which is connected to a first MOS transistor (18) whose gate is controlled by clock signals (V1). A feedback lead (22) from the operational amplifier output (16) is connected to second (24) and third (26) transistors in parallel The second transistor (24) is connected to the input lead between the capacitor and the operational amplifier and the third transistor (26) is connected to the input lead between the capacitor and the first transistor. The gates of the second and third transistors are connected to separate clock signal sources (V3, V2). The timing of the clock signals to the three transistors is such that the Vin signal is sampled and held and the operational amplifier's offset is cancelled.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US7933979A | 1979-09-27 | 1979-09-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
SE8103279L true SE8103279L (en) | 1981-05-25 |
Family
ID=22149901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE8103279A SE8103279L (en) | 1979-09-27 | 1981-05-25 | SAMPLING AND HALLAR CIRCUITS WITH OFFSET ELIMINATION |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS56501223A (en) |
DE (1) | DE3049671A1 (en) |
FR (1) | FR2466838A1 (en) |
GB (1) | GB2075781A (en) |
NL (1) | NL8020352A (en) |
SE (1) | SE8103279L (en) |
WO (1) | WO1981000928A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2534415A1 (en) * | 1982-10-07 | 1984-04-13 | Cii Honeywell Bull | METHOD FOR MANUFACTURING ELECTRICAL RESISTORS IN POLYCRYSTALLINE SEMICONDUCTOR MATERIAL AND RESULTING INTEGRATED CIRCUIT ARRANGEMENT |
NL8501492A (en) * | 1985-05-24 | 1986-12-16 | Philips Nv | SAMPLING AND HOLD SWITCHING DEVICE. |
US4691125A (en) * | 1986-10-03 | 1987-09-01 | Motorola, Inc. | One hundred percent duty cycle sample-and-hold circuit |
GB2214018A (en) * | 1987-12-23 | 1989-08-23 | Philips Electronic Associated | Current mirror circuit arrangement |
US5162670A (en) * | 1990-01-26 | 1992-11-10 | Kabushiki Kaisha Toshiba | Sample-and-hold circuit device |
JP2777302B2 (en) * | 1992-01-16 | 1998-07-16 | 株式会社東芝 | Offset detection circuit, output circuit, and semiconductor integrated circuit |
KR100557501B1 (en) * | 2003-06-30 | 2006-03-07 | 엘지.필립스 엘시디 주식회사 | Analog buffer and method for driving the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3441913A (en) * | 1966-04-12 | 1969-04-29 | James J Pastoriza | Multiple signal sampling and storage elements sequentially discharged through an operational amplifier |
FR96064E (en) * | 1968-10-31 | 1972-05-19 | Ferrieu Gilbert | Sampling device with memory of analog signals. |
US4066919A (en) * | 1976-04-01 | 1978-01-03 | Motorola, Inc. | Sample and hold circuit |
-
1980
- 1980-09-02 DE DE19803049671 patent/DE3049671A1/en active Pending
- 1980-09-02 NL NL8020352A patent/NL8020352A/en not_active Application Discontinuation
- 1980-09-02 WO PCT/US1980/001130 patent/WO1981000928A1/en active Application Filing
- 1980-09-02 JP JP50220380A patent/JPS56501223A/ja active Pending
- 1980-09-02 GB GB8104207A patent/GB2075781A/en not_active Withdrawn
- 1980-09-25 FR FR8020592A patent/FR2466838A1/en active Pending
-
1981
- 1981-05-25 SE SE8103279A patent/SE8103279L/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
GB2075781A (en) | 1981-11-18 |
NL8020352A (en) | 1981-07-01 |
DE3049671A1 (en) | 1982-02-25 |
JPS56501223A (en) | 1981-08-27 |
WO1981000928A1 (en) | 1981-04-02 |
FR2466838A1 (en) | 1981-04-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NAV | Patent application has lapsed |
Ref document number: 8103279-9 |