SE539665C2 - Filling or deep recesses - Google Patents

Filling or deep recesses Download PDF

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Publication number
SE539665C2
SE539665C2 SE1550820A SE1550820A SE539665C2 SE 539665 C2 SE539665 C2 SE 539665C2 SE 1550820 A SE1550820 A SE 1550820A SE 1550820 A SE1550820 A SE 1550820A SE 539665 C2 SE539665 C2 SE 539665C2
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Prior art keywords
substrate
trench
filled
trenches
level
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SE1550820A
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Swedish (sv)
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SE1550820A1 (en
Inventor
Schöner Adolf
Vieider Christian
Reshanov Sergey
Kaplan Wlodzimierz
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Ascatron Ab
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Application filed by Ascatron Ab filed Critical Ascatron Ab
Priority to SE1550820A priority Critical patent/SE539665C2/en
Priority to EP16729551.8A priority patent/EP3311392A1/en
Priority to PCT/EP2016/063608 priority patent/WO2016202787A1/en
Publication of SE1550820A1 publication Critical patent/SE1550820A1/en
Publication of SE539665C2 publication Critical patent/SE539665C2/en

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Physics & Mathematics (AREA)
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  • Crystallography & Structural Chemistry (AREA)
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  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

ABSTRACT A method of manufacturing a semiconductor with very deep dopingStructures, comprising the steps of: a) providing a substrate having anupper surface comprising at least one trench, b) adding material to thesubstrate using epitaxial growth, c) removing material from the top of thesubstrate to a level at or below the original upper surface in step a), d)adding material to the substrate using epitaxial growth, e) removing materialfrom the top of the substrate to a level at or below the level after step c).One advantage is that the method can be performed with fewer epitaxysteps and is thus less expensive and faster. (Fig. 1)

Description

FILLING OF DEEP RECESSES Technical field
[0001] The present invention relates generally to an improved method forfillingrecesses such as trenches and holes for epitaxial grown SiC substrates. lnparticular the invention relates to manufacture deep doping structures by fillingdeep recesses in a SiC substrate by epitaxial growth.
Background[0002] For some applications it is desirable to manufacture filled deep trenches orholes or recesses in a SiC substrate by epitaxial growth.
[0003] A typical example is a substrate of donor-doped SiC where trenches arefilled with acceptor-doped SiC. When a deep filled trench (or hole or recess) is tobe manufactured with epitaxial growth of SiC there is a limitation of the epitaxialgrowth since there is a tendency that the trench (or hole or recess) becomesnarrower due to the epitaxial growth. When the opening of the trench (or hole orrecess) becomes too narrow or even totally closed it is not possible to fill theremaining part of a trench (or hole or recess).
[0004] ln the state of the art this problem is solved by first manufacturing onefirst layer with filled trenches where the trenches are not too deep. Subsequently asecond layer is grown on top of the first layer and then trenches are made in thesecond layer where the position of the trenches is exactly above the filled trenchesin the first layer. When the trenches in the second layer are filled they will be at thesame position as the trenches in the first layer and thus correspond to a deep filledtrench. This process can be repeated with several layers in order to manufacture adesired deep filled trench. The method to grow several layers of alternating donor-doped and acceptor-doped material is time consuming.
[0005] Another strategy in the state of the art is to use ion implantation and growthin layers with epitaxy. This is time consuming because many steps have to beused. The thin layer growth plus ion implantation process has to be repeatedabout 5-times to achieve one layer with filled trench structure as mentioned above.
[0006] Thus it is a problem in the art how to provide a more efficient method to manufacture deep filled trenches in epitaxial grown SiC.
Summag[0007]|t is an object of the present invention to obviate at least some of thedisadvantages in the prior art and provide an improved method to manufacture deep filled trenches in epitaxial grown SiC.
[0008]ln a first aspect there is provided a method of manufacturing a filled trench comprising the steps of: a. Providing a substrate made of a material selected from the groupconsisting of SiC, GaN, and diamond, and having an upper surfacecomprising at least one trench, b. Adding material to the substrate using epitaxial growth, c. Removing material from the top of the substrate to a level belowthe original upper surface in step a), d. Adding material to the substrate using epitaxial growth, e. Removing material from the top of the substrate to a level belowthe level after step c).[0009]ln a second aspect there is provided a filled trench manufactured with the method described above.
[0010]ln a third aspect there is further provided a wafer comprising filled trenchesas described above, wherein the filled trenches cover the entire wafer. Furtheraspects and embodiments are defined in the appended claims, which are specifically incorporated herein by reference.
[0011]One advantage is that the method can be performed with fewer epitaxy steps and is thus less expensive and faster.
[0012]Another advantage is the in-situ alignment between the sequential epitaxialsteps, and thus the avoidance of additional lithographic steps and possible misalignment between the resulting doping structures.
Brief description of the drawinqs
[0013] The invention is now described, by way of example, with reference to the accompanying drawings, in which:
[0014] Fig. 1 shows a schematic view of the method with a donor-dopedmaterial with deep trenches which is filled in two steps with acceptor-dopedmaterial with epitaxial growth with intermediate planarization pl and final planarization pf.
[0015] Fig 2 shows an embodiment with a termination for an embodiment with trenches.
[0016] Fig 3 shows an embodiment with another type of termination for an embodiment with hexagonal structures p.
[0017] Fig 4 shows an embodiment with a different type of termination for anembodiment with hexagonal structures p.
[0018] Fig 5 shows an embodiment with a termination for an embodiment with trenches that are curved at intersections.
[0019] Fig 6 shows an embodiment with a termination for an embodimentwith trenches that are curved at intersections and hexagonal structures.
Detailed description
[0020]Before the invention is disclosed and described in detail, it is to beunderstood that this invention is not limited to particular compounds,configurations, method steps, substrates, and materials disclosed herein assuch compounds, configurations, method steps, substrates, and materials mayvary somewhat. lt is also to be understood that the terminology employedherein is used for the purpose of describing particular embodiments only and isnot intended to be limiting since the scope of the present invention is limitedonly by the appended claims and equivalents thereof.
[O021]|t must be noted that, as used in this specification and the appended claims,the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise.
[O022]|f nothing else is defined, any terms and scientific terminology used hereinare intended to have the meanings commonly understood by those of skill in the art to which this invention pertains.
[0023]ln a first aspect there is provided a method of manufacturing a filled trench comprising the steps of: a. Providing a substrate made of a material selected from the groupconsisting of SiC, GaN, and diamond, and having an upper surfacecomprising at least one trench, b. Adding material to the substrate using epitaxial growth, c. Removing material from the top of the substrate to a level belowthe original upper surface in step a), d. Adding material to the substrate using epitaxial growth, e. Removing material from the top of the substrate to a level belowthe level after step c).[0O24]The removal of material can advantageously be performed by planarization.ln one embodiment step c) is performed with planarization. ln one embodiment step e) is performed with planarization.
[O025]ln one embodiment steps b) to e) are repeated until the trench is completelyfilled. ln some embodiments one performance of steps b) to e) is sufficient to fillthe trench and in this case the steps do not have to be repeated. ln other embodiment the steps b) to e) have to be repeated.
[0026]|n one embodiment the width of the trench is 2 um or more. ln oneembodiment the depth of the trench is 10 pm or more. The filling method issuitable for trenches with high aspect ratio, i.e. trenches which are narrow and deep.
[O027]|n one embodiment 1-2 pm material is removed in step c). Thus the trenchshould be etched 1-2 pm deeper than normal to leave room for an intermediateplanarization or removal of material. lf it is conceived that the structure have tobe planarized and filled several times the trench should be etched evendeeper. As a rule of thumb the trench should be etched 1-2 um deeper for each intermediate planarization (i.e. removal of material in step c)). [0O28]|n a second aspect there is provided a filled trench manufactured with themethod described above.
[0029]|n yet another aspect there is further provided a wafer comprising filledtrenches as described above, wherein the filled trenches cover the entirewafer. This has the advantage that the wafers can be utilized for anyapplication and do not have to be tailored for a specific device. Normally thelayout is dependent on the particular device to be manufactured. Howeverusing this approach one general type of wafers can be used for manufacturingdifferent components varying either in size or design. This approach requirescertain layout or process steps to define the device chip area as well as theedge termination to realize the desired blocking voltage of the device.
[0030]For using devices comprising filled recesses in applications, the processedwafers have to be divided in to chips, where each chip represents one device.Referring to figures 2-4 the wafers are divided in to chips by the dicing lanes(201, 301, 401, 501, 601) representing the edge of the chip. The dicing issuitable done by high speed rotating blades covered with diamond(s). ln figs 2,4, 5, and 6 the dicing is supported by an additional trench etching step (202,402, 502, 602) formed during the device wafer fabrication, in order to have adefined distance between the end of the termination area and the dicing lane.
[0031]ln the case of stripes as in fig 2, the p-stripes pass through the active part ofthe device (203, 204, and 205). Here the p-stripes should not reach the dicinglane (201). Hence, the trench etching (202) is a necessity and the etchedtrench depth should exceed the depth of the p-stripes, to avoid that the p- stripes are cut by the dicing blade. lf the trench etching is done with sloped sidewalls, then one can easily passivate the surface and the end of the p-stripes. The trench (402) is basically not necessary in case of hexagon-structures, because the hexagon cells are not connected to the active part ofthe device. But also here a trench (402 in fig 4) would be beneficial for surface passivation and to define better the edge of the device.
[0032]The metal on the active area (205, 305, 405, 505, and 605) of the device, isone of the connection points of the device to the circuit. The second one in this example is on the backside. Such device is a so called vertical device.
[0033]Further the termination has to be considered. The termination has typicallythe function to lower the electric field at the surface outside the active area of the component. Field plates can be used as termination in one embodiment.
[0034]|n one embodiment, the termination is done by the hexagons, which are notconnected to the active area, as illustrated for instance in fig 3. The terminationprinciple is the same. The depletion region at the surface is extended by the hexagon p-islands to reduce the electric field outside the active device area.
[0035]|n the embodiments illustrated in figs 2, 4, 5, and 6 there are two terminationareas (204, 404, 504, 604 and 203, 403, 503, 603 respectively) shown as anexample. But, depending on the desired blocking voltage, there can be alsoonly one or more than two termination areas. ln one embodiment, when p-stripe design is used (fig 2), the termination areas should be included in thedevice design and should interconnect the p-stripes in a certain area outsidethe active part of the device. ln another embodiment, when hexagon celldesign is used (figs 3 and 4), the termination areas are not necessary, butcould improve the voltage blocking capability of the device. The terminationareas could be formed for example by ion implantation of acceptor dopants.
[0036]All the described alternative embodiments above or parts of an embodimentcan be freely combined without departing from the inventive idea as long as thecombination is not contradictory.
[O037]Other features and uses of the invention and their associated advantageswill be evident to a person skilled in the art upon reading the description and the examples.
[O038]lt is to be understood that this invention is not limited to the particularembodiments shown here. The embodiments are provided for illustrativepurposes and are not intended to limit the scope of the invention since thescope of the present invention is limited only by the appended claims and equivalents thereof.

Claims (9)

1. A method of manufacturing a filled trench comprising the steps of: a. Providing a substrate__§§3_§_ made of a material selected from the groupconsisting ofSiC, GaN, and diamond, and having an upper surfacecomprising at least one trench, b. Adding material to the substrate using epitaxial growth, c. Removing material from the top of the substrate to a level belowthe original upper surface in step a), d. Adding material to the substrate using epitaxial growth, e. Removing material from the top of the substrate to a level belowthe level after step c).
2. The method according to claim 1, wherein step c) is performed withplanarization.
3. The method according to any one of claims 1-2, wherein step e) isperformed with planarization.
4. The method according to any one of claims 1-3, wherein steps b) to e) arerepeated until the trench is completely filled.
5. The method according to any one of claims 1-4, wherein the width of thetrench is 2 um or more.
6. The method according to any one of claims 1-5, wherein the depth of thetrench is 10 um or more.
7. The method according to any one of claims 1-6, wherein 1-2 um material isremoved in step c).
8. A filled trench manufactured with the method according to any one of claims1-7.
9. A wafer comprising filled trenches according to any one of claims 1-7,wherein the filled trenches cover the entire wafer.
SE1550820A 2015-06-16 2015-06-16 Filling or deep recesses SE539665C2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE1550820A SE539665C2 (en) 2015-06-16 2015-06-16 Filling or deep recesses
EP16729551.8A EP3311392A1 (en) 2015-06-16 2016-06-14 Filling of deep recesses
PCT/EP2016/063608 WO2016202787A1 (en) 2015-06-16 2016-06-14 Filling of deep recesses

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SE539665C2 true SE539665C2 (en) 2017-10-24

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3485081B2 (en) * 1999-10-28 2004-01-13 株式会社デンソー Semiconductor substrate manufacturing method
JP3743395B2 (en) * 2002-06-03 2006-02-08 株式会社デンソー Semiconductor device manufacturing method and semiconductor device
CN102956471A (en) 2011-08-19 2013-03-06 上海华虹Nec电子有限公司 Silicon epitaxial filling method for deep trenches

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EP3311392A1 (en) 2018-04-25
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