SE444996B - Databehandlingsanleggning - Google Patents

Databehandlingsanleggning

Info

Publication number
SE444996B
SE444996B SE7900138A SE7900138A SE444996B SE 444996 B SE444996 B SE 444996B SE 7900138 A SE7900138 A SE 7900138A SE 7900138 A SE7900138 A SE 7900138A SE 444996 B SE444996 B SE 444996B
Authority
SE
Sweden
Prior art keywords
data
memory
address
transmission
addresses
Prior art date
Application number
SE7900138A
Other languages
English (en)
Swedish (sv)
Other versions
SE7900138L (sv
Inventor
K D Holberger
J E Samson
Original Assignee
Data General Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Data General Corp filed Critical Data General Corp
Publication of SE7900138L publication Critical patent/SE7900138L/xx
Publication of SE444996B publication Critical patent/SE444996B/sv

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • G06F12/1081Address translation for peripheral access to main memory, e.g. direct memory access [DMA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Systems (AREA)
SE7900138A 1978-01-23 1979-01-08 Databehandlingsanleggning SE444996B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US87169078A 1978-01-23 1978-01-23

Publications (2)

Publication Number Publication Date
SE7900138L SE7900138L (sv) 1979-07-24
SE444996B true SE444996B (sv) 1986-05-20

Family

ID=25357925

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7900138A SE444996B (sv) 1978-01-23 1979-01-08 Databehandlingsanleggning

Country Status (12)

Country Link
JP (1) JPS54121032A (nl)
AU (1) AU526317B2 (nl)
BR (1) BR7900407A (nl)
CA (1) CA1128213A (nl)
CH (1) CH641581A5 (nl)
DE (1) DE2902477A1 (nl)
DK (1) DK157954C (nl)
FR (1) FR2415336B1 (nl)
GB (1) GB2013006B (nl)
IT (1) IT1110622B (nl)
NL (1) NL7900439A (nl)
SE (1) SE444996B (nl)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4459677A (en) * 1980-04-11 1984-07-10 Ampex Corporation VIQ Computer graphics system
US4476527A (en) * 1981-12-10 1984-10-09 Data General Corporation Synchronous data bus with automatically variable data rate
GB2138182B (en) * 1983-04-14 1986-09-24 Standard Telephones Cables Ltd Digital processor
US4607365A (en) * 1983-11-14 1986-08-19 Tandem Computers Incorporated Fault-tolerant communications controller system
US4847750A (en) * 1986-02-13 1989-07-11 Intelligent Instrumentation, Inc. Peripheral DMA controller for data acquisition system
JP2570847B2 (ja) * 1989-02-08 1997-01-16 日本電気株式会社 データ転送方式
CN108241516B (zh) * 2018-02-09 2021-06-18 深圳科立讯通信有限公司 嵌入式***程序加载方法、装置、计算机设备和存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3673576A (en) * 1970-07-13 1972-06-27 Eg & G Inc Programmable computer-peripheral interface
GB1447297A (en) * 1972-12-06 1976-08-25 Amdahl Corp Data processing system
US3976977A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Processor for input-output processing system
JPS522231A (en) * 1975-06-24 1977-01-08 Hitachi Ltd Information processing apparatus
JPS5272543A (en) * 1975-12-15 1977-06-17 Hitachi Ltd Channel equipment of having address converting function
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle

Also Published As

Publication number Publication date
CH641581A5 (de) 1984-02-29
AU526317B2 (en) 1983-01-06
GB2013006B (en) 1982-08-25
CA1128213A (en) 1982-07-20
NL7900439A (nl) 1979-07-25
FR2415336A1 (fr) 1979-08-17
GB2013006A (en) 1979-08-01
AU4322779A (en) 1979-08-02
JPS6259821B2 (nl) 1987-12-12
DE2902477A1 (de) 1979-07-26
BR7900407A (pt) 1979-08-21
FR2415336B1 (fr) 1987-04-24
DK157954C (da) 1990-08-13
DK157954B (da) 1990-03-05
JPS54121032A (en) 1979-09-19
SE7900138L (sv) 1979-07-24
IT7919549A0 (it) 1979-01-23
IT1110622B (it) 1985-12-23
DK3979A (da) 1979-07-24

Similar Documents

Publication Publication Date Title
US4403282A (en) Data processing system using a high speed data channel for providing direct memory access for block data transfers
US5548786A (en) Dynamic bus sizing of DMA transfers
US5381538A (en) DMA controller including a FIFO register and a residual register for data buffering and having different operating modes
US5517627A (en) Read and write data aligner and method
US5448703A (en) Method and apparatus for providing back-to-back data transfers in an information handling system having a multiplexed bus
US4550368A (en) High-speed memory and memory management system
US4161778A (en) Synchronization control system for firmware access of high data rate transfer bus
EP0631241B1 (en) Initializing multiple bus networks
JP4034738B2 (ja) データマスクマッピング情報取得方法
US4169284A (en) Cache control for concurrent access
EP0622737A2 (en) High performance memory system
GB1573539A (en) Digital data processing apparatus
US5448704A (en) Method for performing writes of non-contiguous bytes on a PCI bus in a minimum number of write cycles
WO1997024623A1 (en) Method and apparatus for combining writes to memory
EP1488322B1 (en) Mapping data masks in hardware by controller programming
US4796222A (en) Memory structure for nonsequential storage of block bytes in multi-bit chips
SE444996B (sv) Databehandlingsanleggning
US5146572A (en) Multiple data format interface
US5551009A (en) Expandable high performance FIFO design which includes memory cells having respective cell multiplexors
WO2002077823A1 (en) System and method for building packets
US4964037A (en) Memory addressing arrangement
EP0939374A2 (en) Processor for information processing equipment and control method
JPS6086642A (ja) メモリ制御情報設定方式
US5504871A (en) Memory controller having bus master for addressing instruction memories
EP0365114A2 (en) Interface arrangement for interfacing a data storage device with a data handling system

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 7900138-4

Effective date: 19910805

Format of ref document f/p: F