RU94044339A - Способ изготовления подложки для многослойной интегральной схемы или многокристального модуля и подложка, изготовленная этим способом - Google Patents
Способ изготовления подложки для многослойной интегральной схемы или многокристального модуля и подложка, изготовленная этим способомInfo
- Publication number
- RU94044339A RU94044339A RU94044339/02A RU94044339A RU94044339A RU 94044339 A RU94044339 A RU 94044339A RU 94044339/02 A RU94044339/02 A RU 94044339/02A RU 94044339 A RU94044339 A RU 94044339A RU 94044339 A RU94044339 A RU 94044339A
- Authority
- RU
- Russia
- Prior art keywords
- layer
- substrate
- dielectric
- conductive
- integrated circuit
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract 9
- 238000004519 manufacturing process Methods 0.000 title claims abstract 4
- 238000000034 method Methods 0.000 title abstract 3
- 239000010410 layer Substances 0.000 claims abstract 13
- 239000004020 conductor Substances 0.000 claims abstract 4
- 239000011529 conductive interlayer Substances 0.000 claims abstract 2
- 238000001035 drying Methods 0.000 claims abstract 2
- 238000007789 sealing Methods 0.000 claims 1
- 230000007704 transition Effects 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67236—Apparatus for manufacturing or treating in a plurality of work-stations the substrates being processed being not semiconductor wafers, e.g. leadframes or chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
- H01G4/308—Stacked capacitors made by transfer techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4867—Applying pastes or inks, e.g. screen printing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Способ изготовления подложки для использования в многослойной интегральной схеме или многокристалльном модуле, включающий нанесение проводящего материала 14 на поверхность подложки для формирования проводящей цепи 12 и высушивание листа. Затем нанесение слоя 18 диэлектрика на те места на несущей поверхности, где не нанесен проводящий материал. После этого слой с покрытием уплотняется для формирования уплотненной проводящей цепи, введенной в слой диэлектрика. Второй слой диэлектрика 28 наносят поверх первой уплотненной проводящей цепи, введенной в слой диэлектрика, причем второй слой характеризуется наличием в нем сквозных отверстий 30, которые совмещены по меньшей мере с частью проводящей цепи 12. Сквозные отверстия во втором случае диэлектрика заполняют для формирования электрически проводящих межслойных переходов, затем осуществляется уплотнение для формирования подложки 44.
Claims (1)
- Способ изготовления подложки для использования в многослойной интегральной схеме или многокристалльном модуле, включающий нанесение проводящего материала 14 на поверхность подложки для формирования проводящей цепи 12 и высушивание листа. Затем нанесение слоя 18 диэлектрика на те места на несущей поверхности, где не нанесен проводящий материал. После этого слой с покрытием уплотняется для формирования уплотненной проводящей цепи, введенной в слой диэлектрика. Второй слой диэлектрика 28 наносят поверх первой уплотненной проводящей цепи, введенной в слой диэлектрика, причем второй слой характеризуется наличием в нем сквозных отверстий 30, которые совмещены по меньшей мере с частью проводящей цепи 12. Сквозные отверстия во втором случае диэлектрика заполняют для формирования электрически проводящих межслойных переходов, затем осуществляется уплотнение для формирования подложки 44.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/860.063 | 1992-03-30 | ||
US07/860,063 US5292548A (en) | 1990-04-03 | 1992-03-30 | Substrates used in multilayered integrated circuits and multichips |
Publications (1)
Publication Number | Publication Date |
---|---|
RU94044339A true RU94044339A (ru) | 1996-09-20 |
Family
ID=25332414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU94044339/02A RU94044339A (ru) | 1992-03-30 | 1993-03-30 | Способ изготовления подложки для многослойной интегральной схемы или многокристального модуля и подложка, изготовленная этим способом |
Country Status (8)
Country | Link |
---|---|
US (1) | US5292548A (ru) |
EP (1) | EP0748261A1 (ru) |
JP (1) | JPH07505506A (ru) |
KR (1) | KR950700791A (ru) |
AU (1) | AU3971293A (ru) |
CA (1) | CA2132747A1 (ru) |
RU (1) | RU94044339A (ru) |
WO (1) | WO1993019857A1 (ru) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5534290A (en) * | 1990-04-03 | 1996-07-09 | Visatech Corporation | Surround print process for the manufacture of electrode embedded dielectric green sheets |
JP3099640B2 (ja) * | 1994-06-14 | 2000-10-16 | 株式会社村田製作所 | 焼結体内蔵抵抗体の製造方法及び積層セラミック電子部品の製造方法 |
JP3146872B2 (ja) * | 1994-08-31 | 2001-03-19 | 株式会社村田製作所 | セラミックグリーンシートへの電極形成方法及び積層セラミック電子部品の製造方法 |
US6362737B1 (en) | 1998-06-02 | 2002-03-26 | Rf Code, Inc. | Object Identification system with adaptive transceivers and methods of operation |
US6227658B1 (en) | 1997-06-23 | 2001-05-08 | Kabushiki Kaisha Toshiba | Apparatus and method for forming thin film using ink-jet mechanism |
IT1310557B1 (it) * | 1999-04-02 | 2002-02-18 | Gisulfo Baccini | Apparecchiatura per la produzione di circuiti elettronicimultistrato |
US20030111158A1 (en) * | 2001-12-14 | 2003-06-19 | Murata Manufacturing Co., Ltd. | Method for manufacturing multilayer ceramic electronic element |
US8071695B2 (en) * | 2004-11-12 | 2011-12-06 | Eastman Chemical Company | Polyeste blends with improved stress whitening for film and sheet applications |
US20060174993A1 (en) * | 2005-02-04 | 2006-08-10 | Appleton Coated, Llc | Display with self-illuminatable image and method for making the display substrate and for making the image |
US20100231672A1 (en) * | 2009-03-12 | 2010-09-16 | Margaret Joyce | Method of improving the electrical conductivity of a conductive ink trace pattern and system therefor |
TWI419197B (zh) * | 2010-04-26 | 2013-12-11 | Max Echo Technologies Corp | Production method and process adjustment method of laminated wafer |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1258660A (ru) * | 1969-12-19 | 1971-12-30 | ||
JPS55118654A (en) * | 1979-03-07 | 1980-09-11 | Fujitsu Ltd | Manufacture of high density circuit substrate |
US4586972A (en) * | 1983-04-05 | 1986-05-06 | Matsushita Electric Industrial Co., Ltd. | Method for making multilayer ceramic body |
US4645552A (en) * | 1984-11-19 | 1987-02-24 | Hughes Aircraft Company | Process for fabricating dimensionally stable interconnect boards |
US4753694A (en) * | 1986-05-02 | 1988-06-28 | International Business Machines Corporation | Process for forming multilayered ceramic substrate having solid metal conductors |
US4799983A (en) * | 1987-07-20 | 1989-01-24 | International Business Machines Corporation | Multilayer ceramic substrate and process for forming therefor |
-
1992
- 1992-03-30 US US07/860,063 patent/US5292548A/en not_active Expired - Fee Related
-
1993
- 1993-03-30 EP EP93909215A patent/EP0748261A1/en not_active Withdrawn
- 1993-03-30 JP JP5517646A patent/JPH07505506A/ja active Pending
- 1993-03-30 AU AU39712/93A patent/AU3971293A/en not_active Abandoned
- 1993-03-30 CA CA002132747A patent/CA2132747A1/en not_active Abandoned
- 1993-03-30 RU RU94044339/02A patent/RU94044339A/ru unknown
- 1993-03-30 WO PCT/US1993/002990 patent/WO1993019857A1/en not_active Application Discontinuation
-
1994
- 1994-09-27 KR KR1019940703352A patent/KR950700791A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
KR950700791A (ko) | 1995-02-20 |
EP0748261A4 (en) | 1995-02-15 |
WO1993019857A1 (en) | 1993-10-14 |
JPH07505506A (ja) | 1995-06-15 |
CA2132747A1 (en) | 1993-10-14 |
AU3971293A (en) | 1993-11-08 |
US5292548A (en) | 1994-03-08 |
EP0748261A1 (en) | 1996-12-18 |
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