PL446795A1 - System and method of measuring the reinitialization time of the frequency-code converter counter - Google Patents

System and method of measuring the reinitialization time of the frequency-code converter counter

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Publication number
PL446795A1
PL446795A1 PL446795A PL44679523A PL446795A1 PL 446795 A1 PL446795 A1 PL 446795A1 PL 446795 A PL446795 A PL 446795A PL 44679523 A PL44679523 A PL 44679523A PL 446795 A1 PL446795 A1 PL 446795A1
Authority
PL
Poland
Prior art keywords
auxiliary
counter
main
register
detection system
Prior art date
Application number
PL446795A
Other languages
Polish (pl)
Inventor
Piotr Warda
Original Assignee
Politechnika Lubelska
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Politechnika Lubelska filed Critical Politechnika Lubelska
Priority to PL446795A priority Critical patent/PL446795A1/en
Publication of PL446795A1 publication Critical patent/PL446795A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)

Abstract

Przedmiotem zgłoszenia jest układ i sposób pomiaru czasu reinicjacji licznika przetwornika częstotliwość-kod. Układ do pomiaru czasu reinicjacji licznika (LG) przetwornika częstotliwość-kod (f/N) zawierający w swojej strukturze: system mikroprocesorowy (mP), licznik (LG) z rejestrem stanu bieżącego (RG), układ wykrywania zbocza przebiegu (WZG) i interfejs (I) do wymiany danych z komputerem nadrzędnym (KN), zaś przetwornik częstotliwość-kod (f/N) wyposażony jest w zestaw elementów pomocniczych: licznik pomocniczy (LP), pomocniczy rejestr stanu bieżącego (RP) oraz pomocniczy układ wykrywania zbocza przebiegu (WZP), charakteryzuje się tym, że źródło przebiegu o zmiennym okresie (Tx) dołączone jest jednocześnie do głównego układu wykrywania zbocza (WZG) i pomocniczego układu wykrywania zbocza (WZP). Wyjście głównego układu wykrywania zbocza (WZG) dołączone jest do wejścia sterującego rejestru (RG) stanu bieżącego licznika głównego (LG). Wyjście głównego układu wykrywania zbocza (WZG) dołączone jest do wybranej linii komunikacyjnej systemu mikroprocesorowego (mP). Wyjście pomocniczego układu wykrywania zbocza (WZP) dołączone jest do wejścia sterującego rejestru pomocniczego (RP) stanu bieżącego licznika pomocniczego (LP) oraz wyjście pomocniczego układu wykrywania zbocza (WZP) dołączone jest do wybranej linii komunikacyjnej systemu mikroprocesorowego (mP). Na wejście zegarowe licznika głównego (LG) dołączony jest główny sygnał zegarowy (fclk1) tudzież na wejście zegarowe licznika pomocniczego (LP) dołączony jest pomocniczy sygnał zegarowy (fclk2). Wyjście danych licznika głównego (LG) podłączone jest do wejścia danych rejestru głównego (RG). Wyjście danych rejestru głównego (RG) dołączone jest do wybranego wejścia danych systemu mikroprocesorowego (mP), tudzież licznik główny (LG) podłączony jest z systemem mikroprocesorowym (mP) linią konfiguracyjną (K). Wyjście danych licznika pomocniczego (LP) podłączone jest do wejścia danych rejestru pomocniczego (RP). Wyjście danych rejestru pomocniczego (RP) dołączone jest do wybranego wejścia danych systemu mikroprocesorowego (mP), tudzież do systemu mikroprocesorowego (mP) dołączono linią komunikacyjną interfejs komunikacyjny (I) podłączony linią komunikacyjną z systemem pomiarowym komputera nadrzędnego (KN).The subject of the application is the system and method of measuring the reinitialization time of the frequency-code converter counter. A system for measuring the reinitialization time of a counter (LG) of a frequency-code converter (f/N), containing in its structure: a microprocessor system (mP), a counter (LG) with a current state register (RG), a waveform edge detection system (WZG) and an interface (I) for data exchange with the master computer (KN), and the frequency-code converter (f/N) is equipped with a set of auxiliary elements: an auxiliary counter (LP), an auxiliary current state register (RP) and an auxiliary edge detection system ( WZP), is characterized by the fact that the source of the variable period waveform (Tx) is simultaneously connected to the main slope detection system (WZG) and the auxiliary slope detection system (WZP). The output of the main edge detection system (WZG) is connected to the control input of the register (RG) of the current state of the main counter (LG). The output of the main slope detection system (WZG) is connected to the selected communication line of the microprocessor system (mP). The output of the auxiliary edge detection system (WZP) is connected to the control input of the auxiliary register (RP) of the current state of the auxiliary counter (LP) and the output of the auxiliary edge detection system (WZP) is connected to the selected communication line of the microprocessor system (mP). The main clock signal (fclk1) is connected to the clock input of the main counter (LG), and the auxiliary clock signal (fclk2) is connected to the clock input of the auxiliary counter (LP). The data output of the main counter (LG) is connected to the data input of the main register (RG). The data output of the main register (RG) is connected to the selected data input of the microprocessor system (mP), and the main counter (LG) is connected to the microprocessor system (mP) via a configuration line (K). The data output of the auxiliary counter (LP) is connected to the data input of the auxiliary register (RP). The data output of the auxiliary register (RP) is connected to the selected data input of the microprocessor system (mP), and the communication interface (I) connected to the measurement system of the master computer (KN) is connected to the microprocessor system (mP) via a communication line.

PL446795A 2023-11-22 2023-11-22 System and method of measuring the reinitialization time of the frequency-code converter counter PL446795A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PL446795A PL446795A1 (en) 2023-11-22 2023-11-22 System and method of measuring the reinitialization time of the frequency-code converter counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PL446795A PL446795A1 (en) 2023-11-22 2023-11-22 System and method of measuring the reinitialization time of the frequency-code converter counter

Publications (1)

Publication Number Publication Date
PL446795A1 true PL446795A1 (en) 2024-04-22

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PL446795A PL446795A1 (en) 2023-11-22 2023-11-22 System and method of measuring the reinitialization time of the frequency-code converter counter

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PL (1) PL446795A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150041625A1 (en) * 2013-08-06 2015-02-12 Stmicroelectronics (Research & Development) Limited Time to digital converter and applications thereof
US20160056827A1 (en) * 2014-08-20 2016-02-25 Gerasimos S. Vlachogiannakis Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair
US20210175878A1 (en) * 2019-12-06 2021-06-10 The Regents Of The University Of California Frequency to digital converter, asynchronous phase sampler and digitally controlled oscillator methods

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150041625A1 (en) * 2013-08-06 2015-02-12 Stmicroelectronics (Research & Development) Limited Time to digital converter and applications thereof
US20160056827A1 (en) * 2014-08-20 2016-02-25 Gerasimos S. Vlachogiannakis Fractional-N Frequency Synthesizer Incorporating Cyclic Digital-To-Time And Time-To-Digital Circuit Pair
US20210175878A1 (en) * 2019-12-06 2021-06-10 The Regents Of The University Of California Frequency to digital converter, asynchronous phase sampler and digitally controlled oscillator methods

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
CHING-YUAN YANG, GUANG-KAAI DEHNG, JUNE-MING HSU AND SHEN-IUAN LIU: "in IEEE Journal of Solid-State Circuits, vol. 33, no. 10, pp. 1568-1571, Oct. 1998, doi: 10.1109/4.720406", NEW DYNAMIC FLIP-FLOPS FOR HIGH-SPEED DUAL-MODULUS PRESCALER *
E. ALVAREZ-FONTECILLA, A. I. EISSA, E. HELAL, C. WELTIN-WU AND I. GALTON: "IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 3, pp. 965-974, March 2021", DELTA-SIGMA FDC ENHANCEMENTS FOR FDC-BASED DIGITAL FRACTIONAL-N PLLS *
P. WARDA: "2017 International Conference on Electromagnetic Devices and Processes in Environment Protection with Seminar Applications of Superconductors (ELMECO & AoS), Naleczow, Poland, 2017, pp. 1-4, doi: 10.1109/ELMECO.2017.8267733", MEASUREMENT DATA TRANSMISSION IN THE PRESENCE OF ELECTROMAGNETIC FIELDS *
ŚWISULSKI D, WARDA P: "Energies. 2023; 16(14):5399. https://doi.org/10.3390/en16145399", IMPLEMENTATION OF AN ADAPTIVE METHOD FOR CHANGING THE FREQUENCY DIVISION OF THE COUNTER CLOCK SIGNAL IN A FREQUENCY-TO-CODE CONVERTER *
ŚWISULSKI, D., PAWŁOWSKI, E., DOROZHOVETS, M. (2018).: "In: Mazur, D., Gołębiowski, M., Korkosz, M. (eds) Analysis and Simulation of Electrical and Computer Systems. Lecture Notes in Electrical Engineering, vol 452. Springer, Cham. https://doi.org/10.1007/978-3-319-63949-9_20", DIGITAL PROCESSING OF FREQUENCY–PULSE SIGNAL IN MEASUREMENT SYSTEM *
WARDA P: "Applied Sciences. 2021; 11(21):10341. https://doi.org/10.3390/app112110341", SIMULATION OF AN ADAPTIVE METHOD OF IMPROVING THE ACCURACY AND EXTENDING THE RANGE OF FREQUENCY SIGNAL PROCESSING IN A FREQUENCY-TO-CODE CONVERTER. *
WARDA, P. (2022).: "Informatyka, Automatyka, Pomiary W Gospodarce I Ochronie Środowiska, 12(4), 74–77. https://doi.org/10.35784/iapgos.3258", FREQUENCY-TO-CODE CONVERTER WITH DIRECT DATA TRANSMISSION *

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