PH12014501907A1 - Substrate with enlarged chip island - Google Patents

Substrate with enlarged chip island

Info

Publication number
PH12014501907A1
PH12014501907A1 PH12014501907A PH12014501907A PH12014501907A1 PH 12014501907 A1 PH12014501907 A1 PH 12014501907A1 PH 12014501907 A PH12014501907 A PH 12014501907A PH 12014501907 A PH12014501907 A PH 12014501907A PH 12014501907 A1 PH12014501907 A1 PH 12014501907A1
Authority
PH
Philippines
Prior art keywords
electrodes
carrier substrate
semiconductor chip
webs
receiving areas
Prior art date
Application number
PH12014501907A
Inventor
Walter Siegfried
Ditzel Eckhard
Original Assignee
Heraeus Materials Technology Gmbh And Co Kg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Heraeus Materials Technology Gmbh And Co Kg filed Critical Heraeus Materials Technology Gmbh And Co Kg
Publication of PH12014501907A1 publication Critical patent/PH12014501907A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention relates to a tape-type carrier substrate for mounting a plurality of semiconductor chips comprising an electrically conductive layer structured by cutouts in the layers, wherein the cutouts form a plurality of uniform units in the carrier substrate and each unit comprises a receiving area for mounting at least one semiconductor chip, a residual region and two electrodes for making contact with the semiconductor chip, which are prestructured by the cutouts, wherein the receiving areas are arranged between the electrodes of the same unit and the carrier substrate is formed by a parqueting of the units, in which the receiving areas, the residual regions and the electrodes are connected to one another by webs that are so narrow that, by means of the webs being stamped out using compact stamping tools, the receiving areas can be electrically insulated from the electrodes and the electrodes and receiving areas of the units can be separated from the residual regions, and at least two webs that connect the electrodes to the residual regions are arranged in the region of corners of the unit. The invention also relates to an electronic component comprising two electrodes and a receiving area, produced from such a carrier substrate, in which at least one semiconductor chip is fixed on the receiving area, said at least one semiconductor chip being electrically contact-connected to the electrodes by means of bonding wires. Furthermore, the invention also relates to a method for producing a tape-type carrier substrate and for producing an electronic component.
PH12014501907A 2012-02-29 2014-08-22 Substrate with enlarged chip island PH12014501907A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE102012101645 2012-02-29
DE102012103583.0A DE102012103583B4 (en) 2012-02-29 2012-04-24 Substrate with enlarged chip island and method for its production
PCT/EP2012/005365 WO2013127420A1 (en) 2012-02-29 2012-12-22 Substrate with enlarged chip island

Publications (1)

Publication Number Publication Date
PH12014501907A1 true PH12014501907A1 (en) 2014-11-24

Family

ID=48950709

Family Applications (1)

Application Number Title Priority Date Filing Date
PH12014501907A PH12014501907A1 (en) 2012-02-29 2014-08-22 Substrate with enlarged chip island

Country Status (6)

Country Link
EP (1) EP2820673B1 (en)
CN (1) CN104254916B (en)
DE (1) DE102012103583B4 (en)
PH (1) PH12014501907A1 (en)
TW (1) TWI569393B (en)
WO (1) WO2013127420A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102015102453A1 (en) * 2015-02-20 2016-08-25 Heraeus Deutschland GmbH & Co. KG Ribbon-shaped substrate for the production of chip card modules, chip card module, electronic device with such a chip card module and method for producing a substrate

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3157947B2 (en) * 1993-03-26 2001-04-23 株式会社東芝 Semiconductor device and manufacturing method thereof
US6614102B1 (en) * 2001-05-04 2003-09-02 Amkor Technology, Inc. Shielded semiconductor leadframe package
DE10148120B4 (en) 2001-09-28 2007-02-01 Infineon Technologies Ag Electronic components with semiconductor chips and a system carrier with component positions and method for producing a system carrier
DE10202257B4 (en) * 2002-01-21 2005-12-01 W.C. Heraeus Gmbh Method for fixing chip carriers
US7271471B2 (en) * 2003-06-17 2007-09-18 Dai Nippon Printing Co., Ltd. Metal substrate apparatus, method of manufacturing an IC card module apparatus, and an IC card module apparatus
DE102005044001B3 (en) 2005-09-14 2007-04-12 W.C. Heraeus Gmbh Laminated substrate for the assembly of electronic components
US7656173B1 (en) * 2006-04-27 2010-02-02 Utac Thai Limited Strip socket having a recessed portions in the base to accept bottom surface of packaged semiconductor devices mounted on a leadframe for testing and burn-in
US20080265923A1 (en) * 2007-04-27 2008-10-30 Microchip Technology Incorporated Leadframe Configuration to Enable Strip Testing of SOT-23 Packages and the Like
DE102010005771B4 (en) * 2010-01-25 2012-12-13 Heraeus Materials Technology Gmbh & Co. Kg Modular metal strip, process for its manufacture and component with improved flatness

Also Published As

Publication number Publication date
DE102012103583B4 (en) 2017-06-22
EP2820673B1 (en) 2016-11-16
DE102012103583A1 (en) 2013-08-29
TWI569393B (en) 2017-02-01
TW201338115A (en) 2013-09-16
EP2820673A1 (en) 2015-01-07
CN104254916B (en) 2017-03-08
WO2013127420A1 (en) 2013-09-06
CN104254916A (en) 2014-12-31

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