NZ241402A - Optical subscriber access unit - Google Patents

Description

<div class="application article clearfix" id="description"> <p class="printTableText" lang="en">241402 <br><br> p.-lo.'iv .,,15.I'll <br><br> C <br><br> Ol I 1^4 » «-» «.ii ^ . <br><br> . ..;. AJ:!'%L. ri-- UPVeAollirf^/- ■ <br><br> . .*■cU^^T. ;Ftib'i'j ;;J ■ f&gt; "o: P.O. Joui-i:.!, ,:..; ;TRUE COPY ;N.Z. PATENT OFF! CE ;27 JAN 1992 ;Received ;NEW ZEALAND PATENTS ACT 1953 COMPLETE SPECIFICATION ;"OPTICAL SUBSCRIBER ACCESS UNIT" ;WE, ALCATEL AUSTRALIA LIMITED, A Company of the State of New South Wales, of 280 Botany Road, Alexandria, New South Wales, 2015, Australia, hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: ;I ;24 14 01 ;This invention relates to an optical subscriber access unit for connecting subscriber terminals using asynchronous time-division multiplexing to a telecommunication network. Asynchronous time-division multiplexing enables all kinds of information to be transmitted in a single form comprising packets of bits of fixed 5 length called cells and including a virtual circuit label identifying a call and a virtual circuit group label identifying where applicable a communication circuit group. ;It is known to connect subscriber terminals to a telecommunication network using a subscriber access unit comprising a control unit, a plurality of concentrators, and a switching network connected to the concentrators and to a local central office. 10 The concentrators are provided with subscriber access circuits connected to the subscriber terminals. The switching network is usually some distance from the local central office. The concentrators may be in the immediate vicinity of the switching network or remotely located. ;An all electronic digital subscriber acccss unit is known, for connecting sub-15 scriber terminals using various transmission techniques, including asynchronous time-division multiplexing, to a telecommunication network. The switching network is connected to a digital local ccntral officc and to the control unit by means of asynchronous multiplex links. ;The cells may contain call data or maintenance data or signalling data. When 20 a subscriber is not sending data his subscriber terminal sends empty cells to the concentrator. Reciprocally, if a concentrator has no data to send on a communication channel set up to a subscriber terminal the concentrator sends it empty cells instead. ;In this known type subscriber acccss unit each concentrator comprises subscriber access circuits and two stages of concentration. ;25 Each subscriber access circuit provides functions including: ;2 ;241402 ;- optical-electronic conversion and viec versa for each subscriber terminal connected to the concentrator by an optical fibre line; ;- delineation of the cells received from the subscriber terminal, by which is meant the identification of the start of each cell; ;5 - descrambling of the data field of each cell received from a subscriber terminal; ;- scrambling of the data field of each ccll sent by the concentrator to a subscriber terminal; ;- calculation of the error detection word relating to the header of each cell sent from the concentrator to a subscriber terminal or received from a subscriber terminal; ;10 - re-synchronisation of the cells sent by a subscriber terminal to a local clock of the subscriber access unit; ;- a policing function which monitors the output bit rates of the subscriber terminals; ;- extracting signalling cells from the cells sent by a subscriber terminal and in- ;15 jecting signalling cells into the cells sent by the concentrator to a subscriber terminal; ;- conversion of the virtual circuit and virtual circuit group labels included in each cell sent by a subscriber terminal; ;- calculation of the routing label for routing each ccll in the switching network and insertion of this label in front of the cell header; ;20 - elimination of empty cells sent by a subscriber terminal; and ;- insertion of empty cells into the cells sent from the concentrator to the subscriber terminals. ;The first stage of concentration comprises an asynchronous time-division switching matrix controlled by a microprocessor. The second stage of concentration ;25 comprises another asynchronous time-division switching matrix or a time-division multiplexer/demultiplexer controlled by a microprocessor. ;3 ;241402 ;The design of this subscriber acccss unit is optimised for use of electronic components but is not optimised for use of optical components. These have the advantage of a higher speed and enable spectral multiplexing. Retaining the design of known type subscriber acccss units would result in under use of the performance ca-5 pabilities of optical technology. ;An object of the invention is to propose an optical subscriber access unit whose design is not merely deduced from that of a known electronic subscriber acccss unit but which is optimised for the use of optical components. ;The invention comprises an optical subscriber acccss unit for connecting to a 10 telecommunication network subscriber terminals sending and receiving data in the form of fixed length cells by asynchronous time-division multiplexing, comprising: ;- a switching network connected to a local central office; ;- a control unit connected to the switching network; ;- a plurality of concentrators connected to the switching network; and ;15 - subscriber access circuits respectively connected to the subscriber terminals and to the concentrators; ;said network, said control unit, said concentrators and said line terminals comprising: ;-- means for translating a virtual circuit label or virtual circuit group label in-20 eluded in each cell sent or received by the subscriber access unit and adding to it a routing label for routing said ccll in said subscriber acccss unit; ;-- means for synchronising each ccll sent by a subscriber terminal with a local clock; and ;-- means for implementing a policing function; ;25 wherein the means for translating a virtual circuit label or virtual circuit group label for each cell sent or received by the subscriber access unit and adding a routing ;4 ;241402 ;label to it are located in the switching network and are the same for processing the cells sent or received to or from all subscriber terminals connected to at least one concentrator. ;Preferably, the means for implementing the policing function are located in the 5 switching network and the same policing means are used to process cells received from all the subscriber terminals conncctcd to at least one concentrator. ;This subscriber access unit makes it possible to reduce the number of virtual circuit or virtual circuit group label translator devices, routing label inserter devices and policing devices as these arc common to a large number of subscriber terminals, 10 for example 256 terminals. The cost of a subscriber access unit in accordance with the invention is therefore reduced compared to that which it would have if it were of the same design as a known type subscriber acccss unit. ;In order that the invention will be better understood, embodiments thereof will now be described in relation to the drawings, in which: ;15 Figure 1 shows a block diagram of one embodiment of an optical subscriber access unit in accordance with the invention. ;Figure 2 shows a block diagram of one embodiment of a subscriber access circuit which is part of the embodiment shown in Figure 1. ;Figure 3 shows a block diagram of one embodiment of a concentrator circuit 20 which is part of the example shown in Figure I. ;Figure 4 shows a block diagram of one example of a switching network which is part of the example shown in Figure 1. ;Figure 5 shows a block diagram of one embodiment of a stage included in each concentrator which effects a first level of concentration by non-synchronous statistical 25 spectral and time-division multiplexing. ;5 ;241402 ;Figure 6 shows a block diagram of one embodiment of a stage included in each concentrator which re-synchronises the cells to a local clock of the subscriber access unit. ;Figures 7 and 8 show block diagrams of two embodiments of a stage included in 5 each concentrator which changes the bit rale of cells sent by a the subscriber access circuit to the switching network. ;Figure 9 shows a block diagram of otic embodiment of a stage included in each concentrator which effects a sccond stage of concentration by periodic time-division multiplexing. ;10 Figure 10 shows a block diagram of one embodiment of a switching matrix of the switching network of the embodiment shown in Figure 1. ;Figure 11 shows a more detailed block diagram of this switching matrix. ;Figure 12 shows a block diagram of one embodiment of a time-division demultiplexer stage included in each concentrator which effects a first level of decon-15 centration of the cells sent from this concentrator to a subscriber terminal. ;Figures 13 and 14 show block diagrams (if two embodiments of a bit rate converter stage included in each concentrator to proccss cells transmitted from the concentrator to a subscriber terminal. ;Figure 15 shows a block diagram of one embodiment of a stage included in each 20 concentrator which effects a sccond degree of dcconccntration by spectral demultiplexing of cells sent by this concentrator to a subscriber terminal. ;Figures 16 and 17 show block diagrams of one embodiment of first and second multiplexer/demultiplexers featuring bit rate conversion used to connect a remote concentrator to the switching network. ;25 Figure 18 shows a block diagram of one embodiment of the multiplex part of the first multiplexer/demultiplexer with bit rate conversion. ;6 ;24 1402 ;Figure 19 shows a block diagram of one embodiment of the demultiplex part. Figure 20 shows a block diagram of one embodiment of the bit rate converter part. ;Referring to the drawings, Figure I shows the block diagram of one embodiment 5 of an optical subscriber access unit in accordnncc with the invention. It comprises: ;- terminals LAI through LA256 and LF1 through LF256 respectively connected to subscriber terminals sending and receiving data in the form of fixed length cells by means of asynchronous time-division multiplexing; ;- subscriber access circuits 1 and 6, for example; ;10 - concentrators such as the concentrators 2 and 7; ;- a switching network 5 comprising 128 two-way ports; ;- a control unit 8; ;- multiplexer/demultiplexers 9 for example; and ;- input-output terminals such as the terminal 10 connected to a local central IS office which is part of the main telecommunication network by asynchronous time- ;division multiplexes. ;Each subscriber is connected to a subscriber acccss circuit such as the circuit 1 by a bi-directional monomodc optical fibre offering a bit rate of 622 Mb/s, for example. Each access circuit is conncctcd to an input terminal on a concentrator by an 20 optical fibre offering the same bit rate. The concentrator 2 is conncctcd to 256 subscriber access circuits by 256 lines LB I through LB256, for example. ;There are two categories of concentrator, depending on their distance from the switching network 5. Remote concentrators such as the concentrator 2 are connected to the switching network 5 by a multiplexer/demultiplexer 3, two optical fibres MD1 25 and MD2 and a multiplexer/demultiplexer 4. The multiplexer/demultiplexer 3 is near the concentrator 2 and is conncctcd to it by four bi-directional multiplexes MCI ;7 ;24 1402 ;through MC4. The multiplexer/demultiplexer 4 is near the switching network 5 and is connected to it by four bi-directional multiplexes MT1 through MT4. The multiplexes MCI through MC4 and MTI through MT4 offer a bit rate of 2.67 Gb/s and a load of 0.4 Erlang. The lines M DI, M D2 offer a bit rate of 2.5 Gb/s and a load 5 of 0.8 Erlang, representing the standardised specification of optical fibre transport networks using asynchronous time-division multiplexing. ;The multiplexes of the switching network 5 offer a bit rate of 2.6 Gb/s with a maximal load of 0.4 Erlang. This bit rate has been adopted because it enables the very high speed of optical technology to be exploited and the reduced load of 0.4 10 Erlang makes it possible to rcducc the size of the buffers used in the switching network 5, the reduction in the size of these buffers being very significant if the load is reduced from 0.8 to 0.4 Erlang. However, the transmission systems connecting the remote concentrators to the switching network 5 must have a maximal load compatible with the optimal efficiency of a link, which represents a load of 0.8 Erlang. 15 To exploit the speed of optical technology in the first stages of the subscriber access unit, cells arriving from terminals arc multiplexed at 2.6 Gb/s. This bit rate is the same for all the concentrators so that all can have the same structure irrespective of their distance from the local central office. Transmission between a remote concentrator such as the concentrator 2 and the switching network 5 is therefore 20 handled by a multiplexer/demultiplexer 3 which multiplexes cells from a subscriber terminal in the ratio 2 to 1 and a multiplexer/demultiplexer 4 which demultiplexes the same cells in a ratio 1 to 2. The multiplexer/demultiplexers 3 and 4 naturally effect the converse functions for cells from the switching network and to a subscriber terminal. The multiplexer/demultiplexer 3 also changes the bit rate from 2.6 Gb/s to 25 2.5Gb/s and the multiplexer/demultiplexer 4 cffects the converse change in the bit ;8 ;24 1402 ;rate to match the input-output bit rate of the multiplexer/demultiplexers 3 and 4 to the standardised bit rate of the lines MDI and MD2. ;Concentrators near the switching network 5 such as the concentrator 7 are each connected directly to the network by four bi-directional multiplexes each offering a 5 bit rate of 2.6 Gb/s and a load of 0.4 Erlang. In this example the switching network 5 has 28 two-way ports for 128 multiplexes MT1 through MT128 at the bit rate of 2.6 Gb/s and a load equal to 0.4 Erlang. It can connect 16 concentrators and therefore 4 096 subscriber terminals. The 16 concentrators use 64 ports of the switching network 5. Two other ports are conncctcd to the control unit 8 by two multiplexes 10 and 62 other ports are conncctcd to 31 multiplexer/demultiplexers providing a link to the local central office. Of these, only the multiplexer/demultiplexer 9 is shown by way of example. ;The multiplexer/demultiplexer 9 applies time-division multiplexing to the cells supplied by the switching network 5 and addressed to the main telecommunication IS network, converting the bit rate from 2.6 Gb/s to 2.5 Gb/s because it modifies the cell headers by eliminating the routing label that was needed as far as the output of the switching network 5 but not beyond this point. It modifies the load of the multiplexes outgoing from the switching network 5 by increasing it from 0.4 Erlang to 0.8 Erlang so that is more compatible with the optimal efficiency of transmission lines to the 20 main telecommunciation network. It carries out the opposite conversion for cells incoming from the main telecommunciation network. It raises the bit reate from 2.5 to 2.6 Gb/s by leaving 24 bit periods free before each cell for the subsequent insertion of a routing label. ;In most of the means shown in Figure 1 the functions are implemented by optical 25 circuits but are controlled by electronic circuits, especially the control unit 8, the ;9 ;241402 ;technology of optical memories being as yet insufficiently developed for it to be feasible to substitute optical circuits for all the control electronic circuits. ;Figure 2 shows the block diagram of a subscriber access circuit such as the circuit 1 for example. It comprises two scries of three stages connected in parallel to 5 process the cells from a subscriber terminal and the cells to this subscriber terminal. Cells from a subscriber terminal entering via the two-way line LAI are first processed by a cell delineator stage 21 which identifies the start of each cell. The cells are then processed by a stage 22 which dc-scramblcs the data contained in each cell. It is then processed by a stage 23 which extracts the empty cells sent by the subscriber terminal 10 when there is no data to send. Finally, these cells are sent over the bi-directional line LBl. ;Cells addressed to the subscriber terminal arrive over the bi-directional line LBl and are processed by an empty ccll inserter stage 26 so that each time interval representing a cell is occupied by the transmission of a cell to the subscriber terminal, 15 even if there are no data cells to be sent. The cells, empty or otherwise, are then processed by a data scrambler stage 25. All the cells to be sent to the subscriber terminal are then processed by a stage 24 which calculates an error detection word relating to the header of each cell. Finally, the cells are sent over the line LAI. Scrambling, de-scrambling and error detection word calculation conform to CCITT 20 Recommendation 1432 and arc implemented by optical circuits derived directly from conventional electronic circuits in which optical components having the same respective functions are substituted for the electronic components. Their implementation will therefore be obvious to the man skilled in the art. ;Figure 3 shows the block diagram of a concentrator such as the concentrator 2. 25 It comprises two series of stages in parallel respectively processing cells from and cells to the subscriber access circuits. The cells from 256 subscriber access circuits arriving ;10 ;241402 ;over the 256 lines LBl through LB256 arc first processed by a stage 31 comprising 16 modules 31.1 through 31.16 in parallel. Each of these 16 modules has 16 inputs connected to 16 of the lines LBl through LB256. Take the module 31.1, for example. For 16 lines LBl through LB 16 it cffccts concentration by means of non-synchronous 5 statistical spectral and time-division multiplexing. The module 31.1 supplies on a single optical fibre 32.1 at a bit rate of 622 Mb/s cells encoded by 16 different wavelengths (colours). ;These cells are then processed by a stage 33 which rc-synchronises them to a local clock of the subscriber acccss unit. The stage 33 comprises 16 modules 33.1 10 through 33.16 in parallel. Each of these 16 modules has an input connected to a respective output of a module 31.1 through 31.16. For example, the module 33.1 re-synchronises cells supplied by the module 31.1 over the optical fibre 32.1. From the output of the module 33.1 an optical fibre 34.1 conveys the re-synchronised cells to a spectral multiplexing and bit rate converter stage 35. The stage 35 has 16 inputs 15 connected to the respective outputs of 16 modules 33.1 through 33.16 by 16 optical fibres 34.1 through 34.16. At each input it rcccivcs cclls that can take 16 colours at a bit rate of 622 Mb/s and it restores at a single output cells of 16 colours at 2.6 Gb/s. An optical fibre 36 conveys these cclls to a periodic time-division multiplexing stage 37 to divide the cells between four multiplexes MCI through MC4 at a bit rate of 2.6 20 Gb/s and with a load of 0.4 Erlang. ;The cells are spectrally multiplexed in the stage 31 to divide by 16 the number of modules of the re-synchronisation stage 33. The ceils reconstituted by the stage 33 are spectrally re-multiplexed by the stage 35 to impart 16 different colours to the respective 16 cells received on the 16 inputs of the stage 35. Because of this spectral 25 re-multiplexing it is possible to use a single module in stage 35 to process cells from 16 modules of the stage 33 representing 256 subscriber terminals. ;11 ;24 14 02 ;On the other hand, this spectral multiplexing cannot be retained in the switching network 6. This is why there is provided a stage 37 which substitutes for spectral multiplexing of 16 colours on the optical fibre 36 periodic time-division multiplexing on four optical fibres. The cells sent on these lour fibres representing the multiplexes 5 MCI,..., MC4 can be any colour; these colours arc no longer indicative of spectral multiplexing. ;Cells from the switching network 5 and addressed to 256 subscriber terminals are supplied to a stage 40 by the multiplexes MCI through MC4. The order of these cells has been changed by the switching network 5 so that they can be time-division 10 multiplexed by simple periodic time-division demultiplexing. The stage 40 effects a first degree of deconcentration by means of periodic time-division &amp;dg. and carries out spectral multiplexing to simplify the stages on its output side. ;The cells arriving from the switching network 5 can be any colour. The stage 40 groups them onto a single fibre 41 assigning them 16 different colours. The bit 15 rate of 2.6 Gb/s is retained and as a result cach packet of 16 different colour cells is followed by a gap whose duration is equal to three cell periods. ;A stage 42 then changes the bit rate from 2.6 Gb/s to 657 Mb/s and applies a first degree of spectral demultiplexing. 16 optical fibres 43.1 through 43.16 convey to a stage 44 the cells supplied by the stage 42 and which are spectrally multiplexed 20 using 16 different colours at 657 Mb/s. The stage 44 comprises 16 modules 44.1 through 44.16 in parallel. Each module effects a sccond stage of deconcentration by a second stage of spectral demultiplexing. Each module supplies cells to 16 lines chosen from the 256 lines LBl through LB256. It adjusts the bit rate to 622 Mb/s by eliminating the 24 routing label bits associated with each cell, which are of no 25 further utility beyond this stage 44. ;12 ;241402 ;It is seen that each re-synchronisation module 33.1, ..., 33.16 is on the output side of a spectral and time-division multiplexer module 31.1,..., 31.16, which provides a first level of concentration representing 16 subscriber terminals. Consequently, a subscriber access unit in accordance with the invention requires 16 times fewer re-5 synchronisation modules 33.1 through 33.16 than a known type subscriber access unit. ;Because spectral multiplexing is used the bit rate converter state 35 is common to 256 subscriber terminals. Consequently, a subscriber access unit in accordance with the invention requires 256 times fewer bit rate converter devices than a known 10 type subscriber access unit. ;Thanks to the spectral multiplexing carried out by the stage 40 on the input side of the bit rate converter stage 42, the latter is common to 256 subscriber terminals. On the other hand, it would have to be duplicated 16 times if there were no spectral multiplexing. ;15 By virtue of the spectral multiplexing function which remains up to stage 44, the bit rate conversion function is implemented in each module 44.1 through 44.16 for 16 subscriber terminals. ;Figure 4 shows the block diagram of one embodiment of the switching network 5. It comprises 16 identical deviccs 50.1 through 50.16 each having eight input-20 outputs respectively conncctcd to eight of (he multiplexes MT1 through MT128 to verify the eel! headers, translate the virtual circuity or virtual circuit group label of each cell, insert a routing label in front of the header of each cell, calculate a new error detection word and fulfil the policing function which monitors the bit rate on each call, in other words corresponding to cach virtual circuit or virtual circuit group. 25 It further comprises 24 16x16 switching matrices which are identical and of which 16 (51.1 through 51.16) arc used in an 8x8 bi-directional access configuration ;13 ;24 1402 ;to constitute simultaneously first and third switching stages and eight matrices 53.1 through 53.8 are used folded to offer 16 input-outputs and constitute a second switching stage. ;Each device 50.1 through 50.16 further comprises eight input-outputs connected 5 respectively to eight input-outputs of one of the 16 matrices 51.1 through 51.16. The input-outputs ESI through ES8 represent the rows of the matrix. Each of the matrices is associated respectively with an clcctronic control device 52.1 through 52.16 comprising a microprocessor. Also, the matrices 51.1 through 51.6 each have eight input-outputs ES'l through ES'8 in corresponding relationship to the columns of the 10 matrices and which are connectcd to eight input-outputs of the matrices 53.1 through 53.8 in the following manner: the ith inpul-output of the matrix 53.j is connected to the jth input-output relating to a column of the matrix 51 -i (i varies between 1 and 8 and [ varies between 1 and 16). Each of the matrices 53.1 through 53.8 is associated with a respective control device 54.1 through 54.8 analogous to the control devices 15 52.1 through 52.16. ;Each cell comprises a header of five bytes followed by 48 data bytes when it enters the switching network 5. The header includes a label identifying the virtual circuit of a subscriber, a label identifying any virtual circuit group connecting a plurality of virtual circuits and an error detection word relating to the header. The routing in 20 each switching stage, in particular in the matrices of the switching network 5, is effected by means of a routing label which is joined to the header of each cell. In the subscriber access unit in accordancc with the invention the routing label is inserted at the switching network 5 when a ccll enters the network 5 by means of the devices 50.1 through 50.16. ;25 In this typical embodiment the switching matrices of the network 5 have 16 outputs. Determining the routing at cach stage of the call requires four bits. The ;14 ;241402 ;maximum number of switching stages to be passed through is five, and consequently the routing label must comprise at least 20 bits. There is therefore provision for adding a routing label on three bytes (24 bits) to the header of each cell. This produces cells comprising a larger number of bits and therefore imposes a bit rate 5 change from 2.5 Gb/s to 2.6 Gb/s. The routing labels are deleted and the initial bit rate of 2.5 Gb/s is re-selected in the multiplexer/demultiplexers (9, etc.) which constitute a transmission interface to a local central office of the main telecommunication network. ;Note that the concentrators 2 and 7 offer a bit rate of 2.6 Gb/s even though they 10 do not implement the routing label insertion function. They space out the cells by making provision for subsequent insertion of routing labels by means of the devices 50.1 through 50.16. ;These devices 50.1 through 50.16 group together the functions relating to access to the switching network 5: verification of the header of each cell, translation of the IS label of the virtual circuit or virtual circuit group, insertion of a routing label before the pre-existing header, calculation of a new error detection word applying to all of the new header and the policing function. These functions are located at the entry to the switching network 5 and not in each subscriber access circuit, as was the case with the prior art. They arc common to four multiplex MCI through MC4 which 20 represents 256 terminal subscribers in this embodiment. Consequently, reducing their number makes it possible to rcducc the overall cost of the optical subscriber access unit. ;It is possible to shift these functions to the input of the switching network because asynchronous time-division multiplex switching is a statistical multiplexing 25 process. In particular, the subscriber terminal call concentration function is for statistical multiplexing of cells from lightly loaded subscriber multiplexes to multiplexes ;15 ;k ;# ;24 1 40 ;that have a higher load. As concentration is a simple function of statistical multiplexing, it is possible to shift as far as the entry of the switching network 5 the devices implementing the functions mentioned above. However, this arrangement requires the provision of different virtual circuit labels for all of the 256 subscriber terminals 5 connected to each concentrator. The CCITT provides 16 bits for each virtual circuit label in the cell header so that for the virtual circuit label field there is no problem of assigning different labels to calls representing 256 subscriber terminals connected to the same concentrator. ;A virtual circuit label is assigned to cach call by the control unit 8. This label 10 designates the virtual circuit as assigned to that call on a multiplex in order to route the call either to the local central officc of the subscriber access unit or to a multiplex to another subscriber terminal conncctcd to the same subscriber access unit through the same concentrator or a different concentrator. ;A routing label is assigned to cach cell of a call by the control unit 8 for routing 15 this cell across the switching network 5 or across a concentrator 2, 7, etc. In this latter case the routing label comprises not only information for crossing the switching stages of the switching network 5 but also routing information for crossing the concentrator to which the destination subscriber terminal is connected. To route a call from the switching network 5 to a subscriber terminal requires switching and not 20 only the multiplexing in concentrator stage 44 for cells from the switching network 5 addressed to a subscriber terminal. This will emerge later during the detailed description of the concentrator 2. ;The switching network 5 not only routes each cell to a multiplex connected to the concentrator to which the cell is addressed but also sorts the cells outgoing on each 25 multiplex so that the stage 40 of a concentrator can time-division demultiplex them by means of simple periodic time-division demultiplexing. Twelve bits of the routing ;16 ;2414 02 ;label are used to route each ccll in the three stages of the network 5 and two other bits are used to identify the order of the cclls in a group of four cells on a multiplex. ;The routing bits are read in the control dcviccs 52.1 through 52.16 and 54.1 through 54.8 associated with the matrices 51.1 through 51.16 and 53.1 through 53.8. ;These control devices route and delay the cclls in the matrix queues according to the routing bits. The two bits used to identify the order are assigned to the cells in such a way as to identify the order in which the cclls must leave the switching network 5. ;Figure 5 shows the more detailed block diagram of one embodiment of the module 31.1 from the stage 31 of the concentrator 2 which effects a first concentration of the cells from the subscriber terminals by means of non-synchronous statistical spectral and time-division multiplexing. This module 31.1 comprises a first part consisting of 16 encoders CI through CI6 cach used to encode a cell using a different wavelength chosen from 16 wavelengths, a second part comprising a buffer 76 for writing and reading 16 cells cncodcd using the 16 previously mentioned wavelengths and an electronic control dcvicc 70 including a local clock. ;An input of each encoder CI through CI6 is connected to a respective line LBl through LB 16. An output of each cncodcr is conncctcd to an input of the buffer 76. ;The buffer 76 comprises: ;- an electrically controlled filter 59; ;- a combiner 60 having 16 inputs constituting the inputs of the buffer 76; ;- two three-port couplers 61 and 63; ;- an optical amplifier 62; ;- a two-input combiner 64; ;- two electrically controlled optical gates 65 and 69; ;- two periodic filters 66 and 67; and ;17 ;24 14 02 ;- an optical delay line 68 introducing a time-delay equal to the duration of a cell at 622 Mb/s. ;An output of the combiner 60 is conncctcd to a first port of a coupler 61. A second port of the coupler 61 is conncctcd to an input of the optical amplifier 62. 5 An output of the latter is conncctcd to a first port of the coupler 63. A second port of the latter constitutes the output of the buffer 76 and is connected to an input of the filter 59. The output of the filter 59 constitutes the output of the memory 76 and of the module 31.1. ;A third port of the couplcr 63 is conncctcd to a first end of the delay line 68. 10 A second end of the delay line 68 is conncctcd to two filters 66, 67 in parallel. Each of these two filters covers a band of wavelengths comprising eight of the wavelengths used to encode the cells. These filters can therefore eliminate these 16 wavelengths, in groups of eight. The filter 66 is conncctcd to the optical gate 65. The filter 67 is connected to the gate 69. The outputs of the gates 65 and 69 are connected to the 15 inputs of the combiner 64. An output of the latter is connected to the third port of the coupler 61. ;The electronic control devicc 70 has two outputs connected to respective control inputs of the gates 65 and 69, an output conncctcd to a common control input of each of the encoders CI through C16, an output conncctcd to the module 33.1 and an in-20 put receiving cell detection signals supplied by an output common to the 16 encoders CI through CI6. ;Each encoder, for example the encoder CI, comprises: ;- a cell detector device 71 comprising an optical-part (not shown) through which passes the optical signal conveying the cclls and an electronic part (not shown) capa- ;25 ble of recognising the start of a ccll; ;18 ;24 1402 ;- a delay line 72 delaying the optical signal from the device 71 to give the electronic part of the device 71 and the dcvicc 70 time to carry out their calculations; ;- a wavelength converter 73 having an input receiving an optical signal supplied by an output of the delay line 72, an electrical control input and an output consti- ;5 tuting the output of the encoder and supplying an optical signal to the combiner 60; ;- an electronic AND gate 74; and ;- an electronic control circuit 75 which supplies the control signal for the wavelength converter 73. ;The AND gate 74 has a first input which constitutes the control input of the 10 encoder and receives a control signal supplied by the device 70 to determine the wavelength of the signal leaving the cncodcr, a sccond input connected to an output of the cell detector device 72 which supplies a signal to enable this gate and an output connected to an input of the electronic control circuit 75. The electronic part of the device 71 has an output which supplies a ccll detection signal at the common output 15 of the encoders connected to the input of the control device 70. ;When the device 71 detects a ccll the control device 70 chooses the wavelength with which the cell will be encodcd and sends a message to the common input of the encoders CI through C16. This message is sent in the coder which has received the cell, the AND gate 74 being enabled in this cncodcr by the cell detcctor device 71 and 20 the counterpart gates being disabled in the other encoders. The cell encoded in this way by one colour is stored in the buffer 76. ;The device 70 measures the phase differcncc between the start of each cell and the local clock. It determines the value R of the time-delay to be applied to each cell in order to re-synchronise it with the local clock and then sends this value to the 25 module 33.1 immediately before sending it the relevant cell. ;19 ;24 14 02 ;The buffer 76 operates as follows: it comprises a loop that can store up to 16 cells of 16 different colours. The amplifier 62 regenerates an optical signal each time that it has completed one cycle in the buffer 76. The time-delay introduced by the delay line 76 represents one ccll. Reading one ccll of the 16 cells stored in the buffer 5 is carried out by filtering in the filter 59 so as to read only one cell at a time. The buffer 76 is erased one half at a time, by erasing eight cells encoded on eight wavelengths while eight other cells arc being written on eight other wavelengths. The optical gates 65 and 69 are alternatively opened and closed by the device 70 to carry out this "half and half" writing and erasing. ;10 At this stage the cells from 16 subscriber terminals are concentrated onto the single optical fibre 32.1 by spectral multiplexing on 16 wavelengths but they are not synchronised to the local clock. ;Figure 6 shows the more detailed block diagram of the module 33.1 from the stage 33 of the concentrator 2 for synchronising cclls relative to the local clock. This 15 module 33.1 processes the cells one by one. It comprises: ;- a variable delay line 80 that is adapted to introduce a time-delay between 0 and Tb where Tb is the bit period; ;- two three-port electrically controlled couplers 81 and 85 adapted to route a signal supplied to an input to a choscn one of two outputs; ;20 - nine fixed delay lines 86, ..., 87 88 introducing time-delays equal to Tb,..., ;2pTb, ..., 256.Tb, where £ varies from 0 through 8; ;- eight four-port couplers 82, ..., 83, 84 adapted to be controlled electrically to route a signal supplied to either of two inputs to a chosen one of two outputs; and ;- a control device 79 connected to the control device 70 of the module 31.1 to 25 receive the value R of the time-delay to be applied to each cell. ;20 ;• 24H02 ;The fibre 32.1 is connected to an input of the delay line 80. An output of the line 80 is connected to an input of the couplcr 81. The coupler 81 sends the cells from the delay line 80 either to a first input of the couplcr 82 via the delay line 86 or directly to a second input of the couplcr 82. The latter sends the cells either to its first output 5 or to its second output. When the cclls reach the coupler 83 it sends them either to the first input of the coupler 84 via the delay line 87 or directly to the second input of the coupler 84. The cells arc sent in this way stage by stage to the coupler 85 which has only three ports, a first input conncctcd to the output of the delay line 88, a second input connected directly to another couplcr on its upstream side and an output 10 constituting the output of the stage 33 conncctcd to the optical fibre 34.1. The variable delay line 80 and the couplers 81 through 85 have control inputs connected to respective outputs of the control dcvicc 79. ;Each cell comprises 424 bits at this stage. It is necessary to be able to delay all the bits of a cell by an amount variable between 0 and 424.Tb. As the number 424 15 is between the numbers 256 and 512, the stage 33 comprises nine fixed delay lines of value Tb, 2.Tb, 4.Tb, 8.Tb, 16.Tb, 32.Tb, 64.Tb, 128.Tb, 256.Tb enabling all time-delay values between Tb and 512.Tb to be obtained by the scries combination of some delay lines and short-circuiting the remainder by means of the couplers 82, 83, ..., 84 electrically controlled by the dcvicc 79. The variable delay line 80 provides 20 more refined synchronisation. The cclls outgoing on the fibre 34.1 are therefore synchronised to the local clock ccll period. ;Figure 7 shows the block diagram of a first embodiment 35 a of the spectral multiplexing and bit rate converter stage 35 which operates cell by cell to increase the bit rate from 622 Mb/s to 2.6 Gb/s. At this stage each cell comprises 448 bits because 25 the bit rate conversion also adds a space for 24 routing bits that will be added later to the header of each cell. The stage 35 processes 16 cells simultaneously because the ;21 ;'Ik 14 02 ;16 modules of stage 33 supply it simultaneously with 16 cells encoded by 16 colours which are not necessarily different. For this reason its first function is to apply spectral multiplexing on 16 different colours. ;This embodiment comprises: ;- 16 wavelength converters 89.1 through 89.16 having 16 inputs respectively connected to the 16 fibres 34.1 through 34.16 to assign 16 different colours to the 16 cells supplied by the modules 33.1 through 33.16; ;- a combiner 90 with 16 inputs respectively connected to the 16 outputs of the converters 89.1 through 89.16; ;- an optical amplifier 91; ;- a first set of 424 delay lines 95, 96, ..., 97 cach introducing a time-delay equal to the bit period Tb at 622 Mb/s; ;- a second set of 424 delay lines 105, 106, ..., 107 each introducing a time-delay equal to the bit period T'b at 2.6 Gb/s; ;- 424 three-port couplers 92, 93 94 interleaved between the delay lines of the first set; ;- 424 optical ports 100, 101, ..., 102, 103; ;- a delay line 112 introducing a timc-dclny equal to 24.T'b representing the space left for 24 routing bits; and ;- a control device 111 controlling in parallel all the optical gates 100,..., 103. ;The output of the combiner 90 is connected to the input of the amplifier 91. The output of the latter is connected to the first set of delay lines through the coupler 92. A first output of each of the couplers 92 through 94 is connected to a respective input of the gates 100, ..., 102. The output of the delay line 97 is connected to an input of the gate 103. An output of each of the gates 101,..., 102 is respectively connected to ;22 ;^4 i 4 0 2 ;an input of one of the couplers 108, .... 109. An output of the gate 100 is connected to an input of the delay line 105. ;The set of delay lines 95 through 97 constitutes a first shift register with parallel outputs. The second set of delay lines 105 through 107 constitutes a second shift 5 register having parallel inputs. The gates 100, ..., 103 enable the content of the first register to be transferred to the sccond register. In the first register the bits of the cell are separated by time intervals Tb relating to the bit rate of 622 Mb/s. When a complete cell is present in the first register its bits arc transferred simultaneously into the second register. The bits of this ccll arc separated in the second register by a time 10 interval T'b relating to the bit rate of 2.6 Gb/s. The delay line 112 lengthens each cell by 24 empty bits for the later insertion of 24 routing bits, producing a total of 448 bits per cell. The cell then bccomcs a 2.6 Gb/s ccll and is supplied to the output fibre 34 by the output of the coupler 110. The cclls supplied by this output are in the form of packets of 16 synchronous cells of 16 different colours. Two consecutive packets 15 are separated by a time interval approximately equal to three times the duration of a packet as the bit rate has been multiplied by approximately four. ;Figure 8 shows the block diagram of a sccond embodiment 35 b of the spectral multiplexing and bit rate conversion stage. This embodiment operates on blocks of 16 bits instead of on cclls on 424 bits plus 24 empty bits, which significantly reduces 20 the number of components needed to implement this bit rate converter stage. Each cell of 448 bits is divided into 28 blocks of 16 bits, the 28th block being empty and the 27th block containing only eight wanted bits. The stage 35 b comprises a part 118 which carries out spectral multiplexing, a part 120 which carries out the bit rate conversion on blocks of 16 bits and a part 121 which concatenates the blocks of 16 25 bits after the bit rate conversion. The stage 35 b processes 16 blocks of 16 different colours simultaneously, executing spcctral multiplexing on 16 different colours de- ;23 ;24 U02 ;noted, for example, F11, F12, F13, F14, F21. F44. The part 120 outputs each cell in the form of a string of 28 blocks of bits at 2.6 Gb/s with gaps whose approximate duration is three times the duration of one block, because the bit rate has been multiplied by approximately four. ;The part 121 concatenates these blocks and outputs packets of 16 synchronous cells separated by gaps with an approximate duration of three times the duration of a cell at 2.6 Gb/s. ;The part 118 comprises: ;- 16 wavelength converters 89'. I through 89'. 16 having 16 inputs respectively connected to the 16 fibres 34.1 through 34.16 to assign 16 different colours to the 16 cells supplied by the modules 33.1 through 33.16; and ;- a combiner 90' having 16 inputs rcspcctivcly connected to the 16 outputs of the converters 89M through 89'.16 and an output connected to the part 120 by a single optical fibre 119. ;The part 120 comprises: ;- an optical amplifier 91'; ;- a set of 16 delay lines 95', 96', ..., 97' cach introducing a time-delay equal to one bit period Tb at 622 Mb/s; ;- 16 three-port couplers 92', 93', ..., 94': ;- a second set of delay lines 105', 106' 107' cach introducing a time-delay equal to one bit period T'b at 2.6 Gb/s; ;- 16 three-input couplers 108', ..., 109', 110'; ;- 16 optical gates 100', 101',..., 102', 103'; and ;- a control device 111' controlling in parallel all the optical gates 100' through 103' with a period equal to the duration of 16 bits at 622 Mb/s. ;24 ;241402 ;The design of this part 120 is similar to the design of the stage 35 a described previously but comprises many fewer components and the transfer from the first register to the second register is 28 times faster. On the other hand, the blocks of 16 bits supplied at the output of the part 120 arc separated by gaps in which there is no 5 bit with the result that each cell is no longer a continuous stream of 424 bits. ;The function of the part 121 is to re-establish the continuity of the bits in each cell by concatenating the blocks of 16 bits. The part 121 comprises: ;- a splitter 122; ;- 28 optical gates 123, 124, ..., 126; ;10 . a control device 127 electrically controlling the optical gates 123 through 126 independently of each other; ;- 28 fixed delay lines 127, 128, ..., 129, 130 introducing respective time-delays equal to 0, D, 2.D, 3.DF, ..., 25.D, 26.D where D is the difference between the durations of a block of 16 bits at 622 Mb/s and at 2.6 Gb/s; ;IS - a combiner 131 whose output constitutes the output of the part 121 and of the stage 35; ;- a control device 132; and ;- a delay line 133 introducing a limc-dclay equal to 24.T'b. ;The splitter 122 has 28 outputs respectively connected to 28 inputs of the 20 combiner 131 by 28 gates 123 through 126 in series with one of the delay lines 127 through 130. ;For each cell the first block must be delayed by 27.D, the second by 26.D, and so on. The control device 132 controls the gates 123 through 126 in succession to pass the first block into the delay line 130, the sccond block into the delay line 129, and 25 so on. The 28th block is passed directly by the gate 126 to the combiner 131. At the ;25 ;Lk 1 402 ;output of the combiner 131 cach ccll is again in the form of a continuous stream of 424 bits. Each cell has a different one of 16 colours and is at a bit rate of 2.6 Gb/s. ;Spectral multiplexing using 16 colours provides for very efficient use of the stages 33 and 35 but is not suitable for switching in the switching network 5. The function 5 of the stage 37 is to time-division multiplex these cclls onto four optical fibres to constitute four 2.6 Gb/s multiplexes that arc not spectrally multiplexed. ;Figure 9 shows the block diagram of one embodiment of the stage 37. It receives from the fibre 34 16 synchronous cclls multiplexed by 216 different colours denoted Fll, F12, F13, F14, F21, ..., F41, F42, F43, F44. Each packet of 16 cells is followed 10 by a gap whose approximate duration is equal to three cell periods at 2.6 Gb/s. ;This embodiment comprises: ;- a splitter 140; ;- a periodic filter 141 passing the colours Fll, F21, F31, F41; ;- a periodic filter 142 passing the colours F12, F22, F32, F42; IS - a periodic filter 143 passing the colours F13, F23, F33, F43; ;- a periodic filter 144 passing the colours F14, F24, F34, F44; ;- four delay lines 154 through 157 introducing time-delays equal to 0, Tc, 2.Tc, 3.Tc where Tc is the cell period at 2.6 Gb/s; ;- a combiner 148; ;20 - a splitter 149; ;- a bandpass filter 150 passing the colours F14, F13, F12, Fll; ;- a bandpass filter 151 passing the colours F24, F23, F22, F21; ;- a bandpass filter 152 passing the colours F34,-F33, F32, F31; and ;- a bandpass filter 153 passing the colours F44, F43, F42, F41. ;25 The splitter 140 has four outputs respectively connected to four inputs of the combiner 148 by four channels respectively comprising the filter 141, the filter 142 in ;26 ;241402 ;series with the delay line 155, the filter 143 in series with the delay line 156 and the filter 144 in series with the delay line 157. The output of the combiner 148 is connected to the input of the splitter 149. The splitter 149 has four outputs respectively connected to four outputs of the stage 37 by the respective filters 150 through 153 to 5 provide the multiplexes MCI, ..., MC4. ;The four channels which connect the splitter 140 to the combiner 148 shifts the cells to form four packets of four synchronous cclls. The first channel passes on with no time-delay the cells having the colours Fl I. F2I, F31, F41. The second channel passes on with a time-delay equal to the ccll period the cclls having the colours F12, 10 F22, F32, F42. The third channel passes on with a time-delay equal to two cell periods the ceils having the colours FI3, F23. F33. F43. The fourth channel passes on with a time-delay equal to three ccll periods the cclls having the colours F14, F24, F34, F44. ;The cells having the colours Fl I. F12, F13, F14 having been made successive 15 and contiguous in time, it remains to route them onto a separate multiplex from the cells representing the other 12 colours. The function of the splitter 149 is to split the 16 colour cells to the four filters 150 through 153 which divdc them between four physically separate multiplexes MCI MC4 on four optical fibres. The filter 150 ;passes the four consecutive cclls having I he colours F14, F13, F12. Fll. At the same 20 time, the filter 151 passes the four consecutive cclls having the colours F24, F23, F22, F21. At the same time, the filter 152 At I lie same time, the filter 152 passes the four consecutive cells having the colours F34, F33. F32, F31. At the same time, the filter 153 passes the four consccutivc cclls having the colours F44, F43, F42, F41. ;At the output of the stage 37 the cclls retain their various colours but no longer 25 constitute a spectral multiplex. Each ccll can be distinguished by the time slot and the multiplex conveying it. ;27 ;24 1402 ;Figure 10 shows the block diagram (if one part of the switching network 5 comprising the device 50.1, the matrix 51.1 and the control dcvicc 52.1 associated with the matrix. The matrix 51.1 comprises eight input-outputs ESI, ESS which arc connected to the device 50.1 and eight input-outputs ES'l. ... ES'8 which are respectively con-5 nected to the matrices 53.1, comprises a matrix 180 having 16 inputs for the matrix rows and 16 outputs for the matrix columns. Each input-output ESI, ..., ES8 of the matrix 51.1 is therefore made up of a separate input and output respectively connected to one of the 16 inputs c I,..., c 16 of the matrix 180 and to one of the 16 outputs s I, ..., s 16 of the matrix 180. ;10 The matrix 51.1 further comprises 16 three-port couplers and 16 delay lines enabling four routing bits to be sampled in cach ccll and supplied to the control device 52.1. For example, the input-output ESI is conncctcd to the input c 1 of the matrix 180 by a coupler 166 in scries with a delay line 167 which introduces a time-delay equal to the processing time required for the dcvicc 52.1 to interpret the routing bits. 15 The input-output ESI is also conncctcd directly to the output s 1 of the matrix 180. One port of the couplcr 166 is connected to an input of the control device 52.1 whose block diagram will be described later. ;The device 50.1 comprises eight pairs of 3-port couplers such as the couplers 160, 161, eight pairs of delay lines such as I lie delay lines 162, 163 and eight pairs of 3-port 20 couplers with an electrical control input such as the couplers 164, 165. Each bidirectional multiplex MTI, ..., MT8 is carried in the dcvicc 50.1 by two unidirectional channels with the result that the components of this dcvicc arc duplicated. ;The device 50.1 further comprises: ;- a microprocessor 170; ;25 - an input-output interface 171; ;- a translation memory 172 ;28 ;m ;241402 ;- a signalling memory 173; ;- a policing memory 175; and ;- a bus 174 interconnecting all the above components. ;The cells arriving from subscriber terminals via a concentrator pass in succession ;5 through the coupler 160, the delay line 162 and the couplcr 164. The coupler 160 is a passive coupler whose third port is conncctcd to an input of the interface 171 to send to the latter the five header bylcs of cach ccll. The delay line 162 introduces a time-delay equal to the time required for I he microprocessor 170 to process this header. ;10 The microprocessor 170 chccks this header by recalculating the error detection word and comparing it with that contained in the header, translates the virtual circuit label or virtual circuit group label by consulting the memory 172 which supplies a new label value, adds a routing label to the existing header, calculates a new error detection word to allow for the new virtual circuit or virtual circuit group label and ;15 implements the conventional policing fund ion. The couplcr 164 is an active coupler for inserting a new header into the ccll preceded by three routing label bytes. To this end the coupler 164 has a third port conneclcd lo an optical output of the interface 171 and an electrical control input conncctcd to an output of the interface 171 supplying an electrical enabling signal. ;20 The coupler 164 is also used to send signalling or maintenance cells instead of empty cells. The signalling memory 173 stores signalling cells incoming from or outgoing to the switching network 5, for example signalling cells to or from a control system of the telecommunication network to which the subscriber access unit is connected. ;25 Figure 11 shows a more detailed block diagram of the switching matrix 180 and the associated control dcvicc 52.1. The dev ice 52.1 comprises a microprocessor 200, ;29 ;24 14 02 ;an input-output intcrfacc 201, a routing memory 202, a pointer memory 203, a signalling memory 205 and a bus 204 interconnecting all these components. ;The switching matrix 180 comprises 16 wavelength converters 183, ..., 184, a buffer 181 and a space switching dcvicc 1X2. The converters 183, ..., 184 have 16 5 inputs respectively conncctcd to the 16 inputs c I c 16 of the matrix 180, 16 outputs respectively connected to the 16 inputs of the buffer 181 and 16 elcctrical control inputs respectively conncctcd to outputs of the intcrfacc 201 of the control device 52.1. ;The device 182 executes space switching to transfer each ccll received on one of 10 the 16 inputs e 1, ..., e 16 of the matrix 180 to one of the 16 outputs s 1, ..., s 16 of the matrix 180. ;The function of the buffer 181 is to delay the cclls before they arc transferred into the device 182 as a means of resolving contention problems, that is to say conflict between two cells arriving simultaneously and addressed to the same output of the IS matrix 180. It must be possible to delay in 16 FIFO type queues cclls addressed to any of the 16 outputs s 1, ..., s 16. In the switching matrix 180 the cclls can be assigned 16 different colours by the converters 183 through 184 and the cell colour provides a means of distinguishing between I 6 queues respectively associated with the 16 outputs, while storing the cclls in a set of delay lines common to all these outputs. 20 The 16 queues arc managed by the microprocessor 200 using pointers stored in the pointer memory 203. ;The value of cach pointer is between 0 and k - 1 where k is the number of delay lines in the buffer 181. In this example k — 16. The next ccll to store in a given queue will be written into the delay line of rank q + I if the pointer of this queue is 25 equal to £ and if q is less than k - I. If q = k - 1 the queue is full and this cell will be lost because it cannot be written into the buffer 181. ;30 ;2414 0 2 ;The converters 183, ..., 184 arc electrically controlled by the microprocessor 200 via the interface 201 on the basis of lour bits which the dcvicc 52.1 extracts from the routing label indicating the number of the output to which the ccll is addressed. The colour assigned to the cell represents this output of the matrix 180. 5 The routing memory 202 stores: ;- control parameters of the converters 183, ..., 184 to assign a colour to each cell according to the output to which it is addressed: and ;- an indicator for each ccll showing whether the latter is part of a point-to-point connection or a point-to-multipoint conncction. in which latter ease the routing ;10 memory 202 supplies parameters for tuning a plurality of filters at the output of the device 182. ;The buffer 181 comprises 16 splitters 185...., 186, 272 optical gates PI, ..., P272, 16 combiners 187, ..., 188 and 16 delay lines 189, ..., 190 introducing delays respectively equal to 0, Tc, 2.Tc, 3.Tc, ... 15.Tc where Tc is the cell period. These delay 15 lines can delay any cell by an amount between 0 and 15.Tc independently of the ccll colour. The splitters 185, ..., 186 cach have an input constituting a respective one of the 16 inputs of the buffer 181 and 17 outputs respectively connected to one of the 272 optical gates PI, ..., P272. ;Of the 17 outputs of cach splitter. 16 arc conncctcd by these gates to a respective ;20 input of one of the 16 combiners 187 I8X and the seventeenth output is connected by a gate to one input of the input-output interface 201 of the control dcvicc 52.1. This input of the intcrfacc 201 is provided with an optical-electronic converter device (not shown) and enables the microprocessor 200 to receive the content of the signalling cells. Each input of cach of the combiners 187, ..., 188 is therefore connected by 25 one of the gates PI, ..., P272 to an output of one of the splitters 185, ..., 186. Thus any ccll arriving at any one of the 16 inputs of the matrix 180 can be passed through ;31 ;24 1402 ;any one of the 16 combiners, 187 188 by opening one of the gates PI, ..., P272 ;which are controlled independently of cach other by the microprocessor 200 via the interface 201. ;Each combiner 187, ..., 188 has an output conncctcd to one of the delay lines 5 189, ..., 190. The control dcvicc 52.1 therefore dccidcs to delay by an amount between 0 and 15.Tc each of the cclls arriving on one of the 16 inputs of the matrix 180 according to pointers contained in the memory 203 enabling the flow of cclls addressed to each of the 16 outputs to be monitored and the time-delay assigned to each cell to be determined. The buffer 181 behaves like 16 FIFO queues for the 16 outputs 10 of the memory 180. ;The number of cells that can be stored in cach queue is set by the number k of delay lines 189, ..., 190. In this example this number is 16. The article "Buffer Sizing in an ATM Switch for both ATM and STM traffics", International Journal of Digital and Analog Cabled Systems, vol 2, 247-252 (1989) shows that an output buffer hav-15 ing a capacity of 16 cclls for cach output makes it possible to achieve a ccll loss rate equal to 101 °. It is possible to obtain a given loss figure by choosing the number k of delay lines 189, ..., 190. ;In this embodiment the matrices 51.1 through 51.16 of the switching network 5 also change the order of the cclls addressed to a concentrator, the order required bc-20 ing indicated by two routing bits. To achieve a given order at the output of the matrix, the cells must be read in this order inside the buffer 181. The queue of cach output multiplex is managed by the microprocessor 200 like four independent "sub-queues" respectively adapted to store the cclls ranked I, 2, 3, 4. ;Consider the queuing of four cclls which arc to be sent in the order CI, C2, C3, 25 C4 to a given output of the matrix 181 although they arrive at the inputs of the matrix 181 in the order C2, CI, C4, C3, for example. The cell C2 is written into the ;32 ;241402 ;second sub-queue, the ccll CI is written into the first sub-queue, the cell C4 is written into the fourth sub-queue and the ccll C3 is written into the third sub-queue. The write sub-queue is choscn from the four pciuiing sub-queues for a given multiplex by the two routing bits indicating the rank of ench ccll. The read sub-queue is chosen 5 periodically: first, then second, then third, then fourth, etc. ;The space switching dcvicc 182 comprises: ;- a combiner 191 having 16 inputs respectively conncctcd to the 16 outputs of the buffer 181 and formed by the outputs of the 16 delay lines 189,..., 190; ;- an optical amplifier amplifying the optical signal supplied by an output of the 10 combiner 191; ;- a splitter 193 having one input conncctcd to the amplifier 192 and 16 outputs; ;and ;- 16 filters 194, ..., 195 each having an input connected to a respective output of the splitter 193, an electrical control input connccted to an output of the interface ;15 201 and selecting one of 16 colours and an output constituting one of the 16 outputs s 1, ..., s 16 of the switching matrix ISO. ;The combiner 191, the amplifier 192 and the splitter 193 enable all of the cells leaving the buffer 181 to be applied to the 16 filters 194, control signal supplied to it by the control dcvicc 52.1 for cach cell period. They arc usually controlled in such a 20 way that each filters a different colour to route a ccll from a point to a uniquely defined other point. In some cases, for example to broadcast a message simultaneously to multiple addressees, these filters can be commanded to filter the same colour in a plurality of filters representing a plurality of addressees of the same cell. ;Figure 12 shows the block diagram of the spectral multiplex and time-division 25 demultiplex stage 40 of the concentrator 2. It receives on the four multiplexes MCI, ..., MC4 cclls with any colour at a bit rate of 2.6 Gb/s. It outputs on a single optical ;33 ;24 1 402 ;fibre 41 packets of 16 synchronous cclls by spcctral multiplexing using 16 different colours at 2.6 Gb/s. Two consccutivc packets of 16 cclls arc separated by a gap whose duration is equal to three ccll periods. This stage comprises: ;- four wavelength converters 245 through 248 having four inputs respectively 5 connected to the four multiplexes MCI MC4; ;- a combiner 249 having four inputs respectively conncctcd to four outputs of the converters 245 through 248; ;- a splitter 250 having an input conncctcd to the output of the combiner 249 and four outputs; ;10 - four electrically controlled optical gates 251 through 254; ;- a set of four delay lines 255 through 257 introducing respective time-delays equal to 0, Tc, 2.Tc, 3.Tc where Tc is the cell period at 2.6 Gb/s; ;- a combiner 262 having four inputs anil an output constituting the output of the stage 40 connected to the fibre 41; and ;15 - a control device 263 controlling cach of the gates 251 through 254 independently and controlling each of the converters 245 through 248 independently. ;Each output of the splitter 250 is respectively connected to an input of the combiner 262 by a gate 251,..., 254 and a delay line 255, ..., 258. ;Consider time-division demultiplexing: ;20 - a packct of four consccutivc cclls CI. C2. C3, C4 arriving on multiplex MCI; ;- a packct of four consccutivc cclls C5. C6. C7, C8 arriving on multiplex MC2; ;- a packet of four consccutivc cclls Cl), C10, CI I, CI2 arriving on multiplex MC3; and ;- a packct of four consccutivc cclls CI3, CI4, CI5, CI6 arriving on multiplex 25 M.C4; ;these four packets arriving simultaneously. ;34 ;24 1402 ;The four cells from cach packct arc coloured in succcssion by one of the converters 245 through 248 so that 16 different colours arc assigned to the cclls CI through CI6. The colours arc assigned periodically at intervals of four ccll periods. ;The four cells of cach packct arc time-delayed by respective amounts equal to 5 0, Tc, 2.Tc, 3.Tc in order to make them synchronous with each other. To this end each gate 251 and 252 is opened in turn for I lie duration of a ccll and periodically with a period equal to four ccll periods Tc. Thus the cclls C4, C8, C12, CI6, for example, are sent simultaneously by the gate 254 and arc delayed simultaneously by the delay line 258 which introduces a time-delay equal to 3.Tc. They reach the combiner 10 262 at the same time as the cclls CI. C5. CLK CI 3, for example which are transmitted simultaneously by the gate 251 and which arc transmitted with a null time-delay by the line 255. ;Figure 13 shows the block diagram of a first embodiment 42 a of the bit rate converter stage 42 of the concentrator 2. This embodiment operates ccll by cell in an 15 analogous manner to the stage 35n shown in Figure 7 and previously described. It processes 16 cells simultaneously, receiving simultaneously 16 synchronous cells spectrally multiplexed using 16 different colours. ;Each cell comprises 424 bits plus 24 routing label bits, or 448 bits in all, at this level of the concentrator 2. The bit rate is therefore 657 Mb/s. ;20 The stage 42 a comprises: ;- a first series of 448 delay lines 233 234 cach introducing a time-delay T'b equal to the bit period at 2.6 Gb/s: ;- a first series of 448 three-port couplers 230, 231, ..., 232 interleaved into the first series of delay lines on the input side of cach of these lines, respectively; ;25 - a second scries of 448 delay lines 23(&gt; 240 cach introducing a time-delay equal to Tb', the bit period at 657 Mb/s; ;35 ;24 1402 ;- a second series of 448 three-port couplers 241,242, 243 interleaved into the second series of delay lines at the output of each of these lines; ;- 448 electrically controlled optical gates 235, 236, ..., 237; ;- a control device 244 having an output controlling simultaneously all the optical 5 gates 235, 236, 237, 238; ;- a splitter 210 with 16 outputs: and ;- 16 filters 211,..., 212 respectively limed to the 16 ceil colours having 16 inputs respectively connected to the 16 outputs of the splitter 210 and 16 outputs constituting the 16 outputs of the stage 42 a connected to the fibres 43.1, ..., 43.16. ;10 The optical gate 235 connccts a third port of the couplcr 230 to the input of the display line 239. The optical gate 236 connccts a third port of the couplcr 231 to the third port of the coupler 241 at the output of the delay line 239, etc. The optical gate 237 connects a third port of the couplcr 232 to the third port of the coupler 242 at the input of the delay line 240. The optical gale 238 connccts the output of the last delay 15 line 234 of the first series of delay lines to the third port of the couplcr 243 at the output of the last delay line 240 of the second series of delay lines. One port of the coupler 230 constitutes the input of the stage 42a and is connccted to the optical fibre 41. A port of the coupler 243 is conncctcd to an input of the splitter 280. ;The two series of delay lines arc used like two shift registers. When a complete 20 cell is stored in the first scries of delay lines 233. ..., 234 the control dcvicc 244 simultaneously commands all the optical gates 235, 238 to transfer 448 bits simultaneously into the second series of delay lines. The bits arrive at the first series of delay lines 230 through 234 at 2.6 Gb/s and leave the second series of delay lines 239 throgh 240 at 657 Mb/s as they arc separated by a time-delay equal to Tb'. The splitter 210 25 and the filters 211,..., 212 spcctrally demultiplex cach packct of 16 cells onto 16 output optical fibres 43.1 through 43.16. ;36 ;241402 ;Figure 14 shows the block diagram of a sccond embodiment 42 b of the bit rate converter stage 42 in the concentrator 2. Tiiis sccond embodiment is an optimised variant of the first embodiment 42 The two series of 448 delay lines arc replaced by two series of 16 delay lines to apply bit rate conversion in blocks of 16 bits rather 5 than cell by cell, with a view to simplifying the implementation. However, the cells must be divided into 28 blocks of 16 bits first. The stage 42 b therefore comprises a first part 220 dividing cach ccll into 2K blocks of 16 bits, a second part 221 carrying out the bit rate conversion block by block and a third part 222 comprising a splitter 280' and 16 filter 281', ..., 282' for spectrally demultiplexing cach packct of 16 cells 10 onto 6 output optical fibres 43.1 through 43.16. ;The first part 220 comprises: ;- a splitter 270 having an input conncctcd to the optical fibre 41 supplying cells at 2.6 Gb/s and having 28 outputs; ;- a combiner 280 having an output constituting the output of the first part 220 15 which is connected to an input of the sccond part 221 and 28 inputs; ;- 28 electrically controlled optical gales 271, 272. ..., 273, 274; ;- 27 delay lines 275, ..., 276. 277. 27S introducing time-delays respectively equal to 27.D, 26.D, ..., D, 0 where D is the difference between the duration of a block of 16 bits at 657 Mb/s and its original duration at 2.6 Gb/s; and ;20 - a control device 279 having outputs icspcctively conncctcd to control inputs of the optical gates 271,..., 274. ;27 outputs of the splitter 270 arc respectively conncctcd to one of the 28 inputs of the combiner 280 by a channel comprising an optical gate in series with a delay line. ;25 The control device 279 successively opens the gates 271, ..., 274 to pass successively the 28 blocks of 16 bits constituting cach ccll. A first block is passed without ;37 ;241402 ;any time-delay by the gate 274 and the direct connection. A second block is passed by the gate 273 to be stored and delayed in I he delay line 277 introducing a time-delay representing a block of 16 bits. A third block is passed by a gate (not shown) into a delay line (not shown) introducing a lime-delay representing two blocks of 16 5 bits, and so on. The 28th block is passed bv the gate 271 to be stored in the delay line 275 for a duration representing 27 blocks of 16 bits. The first part 220 therefore passes blocks of 16 bits to the sccond part 221 and spaces them by a time-delay representing the duration of 16 bits at 657 Mb 's. so that cach block can be processed in the part 221 because the time available is equal to the duration of a block of 16 10 bits at 657 Mb/s. ;The design of the part 221 is similar to that of the first embodiment 42 a described previously and shown in Figure 14 except that the number of delay lines of the first series 223',..., 234', the number of couplers 230',..., 232' interleaved into the first series of delay lines, the number of optical gates 235', ..., 238', the number of ;15 delay lines of the second series 239' 240'. and the number of couplers 241',..., 243' ;interleaved into the second scries of delay lines is equal to 16 instead of 448 in each case. Consequently this bit rate converter stage 42 b is much easier to implement than that of the stage 42 a previously described. ;The splitter 210' and the converters 211' 212' have the same functions as the ;20 components with the same rcfercncc numbers in the embodiment 42 sl ;Figure 15 shows the block diagram of one embodiment of a module 44.1 of the stage 44 which provides a sccond stage of deconcentration by spectral demultiplexing and bit rate adjustment, it comprises: ;- a three-port couplcr 289; ;25 ;38 ;m ;241 A 02 ;- a bit rate adjuster dcvicc 295 which eliminates the three routing label bytes and changes the bit rate from 657 Mb/s to 622 Mb/s to re-establish the continuity of the bits following elimination of the routing header; ;- a wavelength converter 296 having an clcctrically controlled input; 5 - a 16 output splitter 297; ;- 16 filters 298, ..., 299 respectively passing 16 fixed wavelengths and having outputs which constitute the 16 outputs of the module 293 conncctcd to the lines LBl, ;LB 16; and ;- a routing label extractor dcvicc 288. ;10 The coupler 289 has three ports: n first port constitutes the input of the module 44.1, a second port is conncctcd to an input of the bit rate adjuster device 295 and a third port is connected to an input of the routing label extractor dcvicc 288. This is a conventional design and its function is to control the wavelength converter 296 by supplying to it an electrical signal which sclccts a colour so as to impart to a cell a 15 colour representing the contcnt of its routing label. The output of the devicc 295 is connected to the input of the wavelength converter 296. The output of the latter is connected to the input of the splitter 297. The 16 outputs of the splitter 297 arc respectively connected to the inputs of the 16 filters 298,..., 299. The filter representing the wavelength of a ccll passes that ccll to ;i subscriber terminal. ;20 The bit rate adjuster dcvicc 295 will not be dcscribcd in detail. Its design is similar to that of the part 120 of the stage 35b dcscribcd previously and shown in Figure 8. The man skilled in the art. will know how to adapt this design to effect a change of bit rate from 657 Mb/s to 622 Mb/s. ;Figure 16 shows the block diagram of one embodiment of the 25 multiplexer/dcmultiplexcr/bit rate converter 3. It comprises: ;39 ;24 1 402 ;- four bit rate converter dcviccs D1 through D4 receiving the cclls from the concentrator 2 via the multiplexes MCI through MC4 at 2.6 Gb/s and outputting these cells at 2.5 Gb/s; ;- a statistical multiplexer 350 receiving the cclls output by the dcviccs Dl ;5 through D4 on four inputs and outputting on two outputs time-division multiplex cells such that the load of cach multiplex is modified from 0.4 to 0.8 Erlang, these cells being then conveyed by the multiplexes MDl and MD2 to the multiplexer/demultiplexer 4; ;- a demultiplexer 351 receiving on two inputs cells supplied via the multiplexes ;10 MDl and MD2 at 2.5 Gb/s and having a maximal load of 0.8 Erlang and outputting demultiplexed cells on four outputs, cach multiplex having a load of only 0.4 Erlang; and ;- four bitrate converter dcviccs D5 though D8 receiving the cclls demultiplexed by the demultiplexer 351 at 2.5 Gb/s and outputting them to the multiplexers MCI ;15 through MC4 at 2.6 Gb/s. ;Figure 17 shows the block diagram of one embodiment of the multiplexer/demultiplexer/bit rate converter 4. It comprises: ;- a demultiplexer 352 receiving cells supplied by the two multiplexes MDl, MD2 at 2.5 Gb/s and having a maximal load of 0.S Erlang and outputting on four outputs ;20 demultiplexed cclls at a bit rate of 2.5 Gb s and having a maximal load of 2.4 Erlangs; ;- four bit rate converter dcviccs D9 through DI2 respectively connected to the four outputs of the demultiplexer 352 to receivc demultiplexed cells at 2.5 Gb/s to change their bit rate to 2.6 Gb/s and to supply them to the multiplexes MTI through ;25 MT4; ;40 ;1 ;24 1402 ;- four bit rate converter dcviccs DI3 through D16 respectively receiving cells supplied by the four multiplexes MT1 through MT4 at 2.6 Gb/s and having a maximal load of 0.4 Erlang and restoring Ihem ;it 2.5 Gb/s; and ;- a statistical multiplexer 353 receiving on four input cclls reconstituted by the 5 devices D13 through D16 and time-division multiplexing them to output them via two outputs to the two multiplexes MDl and MD2 at 2.5 Gb/s with a maximal load of 0.8 Erlang. ;Figure 18 shows the block diagram of one embodiment of the multiplexer 350. It comprises; ;10 - four wavelength converters 300 through 303 cach having a first input receiving cells respectively supplied by the four bit rate converter devices D1 through D4; ;- a combiner 304 having four inputs respectively conncctcd to four outputs of the converters 300 through 303; ;- a buffer 305 having a first input conncctcd to the output of the combiner 304; 15 - a splitter 306 having an input connected to the output of the buffer 305 and three outputs one of which is conncctcd to a sccond input of the buffer 305; ;- two electrically controlled filters 307 and 308 having inputs respectively connected to two outputs of the splitter 306 ami two outputs respectively conncctcd to the two multiplexes MDl, MD2: and ;20 - an electronic control dcvicc 30l) liming outputs respectively conncctcd to control inputs of the converters 301, .... 303, a control input of the buffer 305 and control inputs of the filters 307 and 308. ;The design of the buffer 305 is similar to that previously dcscribcd for the stage 31 of the concentrator 2 and shown in Figure .5. It comprises: 25 - a three-port couplcr 310 a first port of which constitutes the first input of the buffer 305; ;41 ;a ;241402 ;- an optical amplifier 311 having an input conncctcd to a sccond port of the coupler 310 and an output constituting the output of the buffer 305; ;- a combiner 12 having an output conncctcd to the third port of the couplcr 310; ;- two electrically controlled optical gates 313 and 314 whose outputs are re- ;5 spectively connected to two inputs of the combiner 312 and which have control inputs connected to outputs of the electronic control dcvicc 309; ;- two periodic filters 315 and 316 having outputs respectively connccted to inputs of the gates 313 and 314: and ;- a delay line 317 introducing a time-delay representing the duration of a cell 10 comprising 424 bits at 2.5 Gb/s whose output is conncctcd to a common input of the filters 315 and 316 and whose input constitutes a sccond input of the buffer 305 and which is connected to an output of the splitter 306. ;The components 310 through 317 constitute a loop which can store up to 16 cells coded by 16 different colours assigned by means of the converters 300,..., 303. The IS electronic control device 309 knows at all times the number and the colours of the cells stored in the buffer 305. A particular ccll is read by tuning one of the filters 307, 308 to the colour of that ccll. The dcvicc 300 then commands the erasing of that cell in the buffer 305 by means of an erasing system comprising the components 312 through 316. The filter 315 erases eight of the 16 possible colours and the filter 316 20 erases the other eight colours. The dcvicc 30") sclccts the filter 315 or the filter 316 by opening one of the two optical gates 313. 314. When both optical gates arc open none of the colours is eliminated and 16 cclls of 16 different colours can therefore circulate in the loop in which they arc regenerated by the amplifier 311. An alternative implementation of the erasing system comprises two electrically controlled filters 25 instead of the fixed filters 315, 316 and the gates 313, 314. ;42 ;241402 ;The statistical multiplexer 353 of the imilliplcxcr/clcmultiplexcr/bit rate converter 4 may be implemented in the same way as I he multiplexer 350 dcscribcd above. ;Figure 19 shows the block diagram of one embodiment of the demultiplexer 351. It comprises: ;5 - two wavelength converters 330. 331 having inputs respectively connccted to the two multiplexes MDl, MD2; ;- a combiner 332 having two inputs respectively conncctcd to the outputs of the converters 330, 331; ;- a buffer 333 identical to the buffer 305 previously dcscribcd having a first in-10 put connected to an output of the combiner 332: ;- a splitter 334 having an input conncctcd to an output of the buffer 333 and five outputs one of which is conncctcd to a sccond input of the buffer 333; ;- four electrically controlled filters 335 through 33B cach having an input connected to a respective output of the splitter 334 and an output connccted to the re- ;15 spective input of one of the bit rate converter circuits D5 through D8; and ;- an electronic control dcvicc 339 having outputs connccted to respective control inputs of the wavelength converters 330. 331. the buffer 333 and the filters 335 through 338. ;The cells supplied by the multiplexes MDl and MD2 with a maximal load of 0.8 20 Erlang arc assigned a colour choscn from l(&gt; colours by means of the wavelength converters 330 and 331 in order to store up to 16 different colour cclls in the buffer 333. The control dcvicc 339 knows at all limes the numbers and the colours of the cells stored in the buffer 333. It commands reading of the stored cclls in order to send them in succession to the bit rate converter devices D5 through D8 by commanding 25 the filters 335 through 338 to pass a selected ccll to one of the outputs of the demultiplexer 351. When eight cclls have been read in the buffer 333 the control de- ;43 ;241402 ;vice 339 commands the erasing .system to erase the cclls of these eight colours from the buffer 333. ;Figure 20 shows the block diagram of a bit rate converter circuit, for example the circuit D5. It comprises: ;5 - a splitter 360 having an input conncctcd to the output of the demultiplexer 351 ;to receive cells at 2.5 Gb/s and n outputs where n is the number of bits in a cell, which is equal to 424 in the case of the circuit D5: ;- (n - 1) delay lines 361, 362 363 introducing time-delays respectively equal to (n - l).TbI, (n - 2).Tbl, ..., Tbl cach having an input conncctcd to a respective ;10 output of the splitter 360, Tbl being the bit period before the bit rate is changed, that is say the bit period at 2.6 Gb/s for the circuit CI; ;- n electrically controlled optical gates 364, 365, ..., 366 cach having an input connected to the respective output of one of the delay lines 361, 362, ..., 363 and a gate 367 having an input conncctcd dircctly to an output of the splitter 360; ;15 - n delay lines 368, ..., 369, 370 respectively introducing time-delays equal to Tb2,..., (n - 2).Tb2, (n - l).Tb2 each having an input conncctcd to a respective output of the gates 365, ..., 366, 367 where Tb2 is I he bit period for the new bit rate which is 2.5 Gb/s for the circuit D1; ;- n additional delay lines 371. 372 373. 374 cach introducing a time-delay ;20 equal to m.Tb2 where m is the number of routing label bits which is 24 in this subscriber acccss unit; ;- a combiner 375 having an input conncctcd dircctly to the output of the gate 364, n - 1 inputs conncctcd to the rcspcctivc outputs of the additional delay lines 371, 372, ..., 373, 374 and an output constituting the output of the circuit D5 which is ;25 connected to the multiplex MCI and supplies it with cclls at a new bit rate of 2.6 Gb/s; and ;44 ;Ik 1 4 o ;- an electronic control device 376 having an output connected to control inputs of the gates 364, 365, 366, 367. ;The n outputs of the splitter 360 arc therefore all conncctcd to an input of one of the gates 364, 365, ..., 366, 367 hv n delay lines whose time-delays run from 0 5 through(n - l).Tbl in steps of Tbl. Consequently, n bits of the same cell arrive at the input of these gates simultaneously. The control dcvicc 376 then opens all the gates 364 through 367 simultaneously to transfer ihcsc n bits into the other series of delay lines representing the bit duration Tb2 at the sccond bit rate. The output of the gate 364 is connected directly to the input of the additional delay line 371. The outputs 10 of all the other gates 365, ..., 366, 367 are connected to the respective inputs of the additional delay lines 372, ..., 373, 374 by a set of delay lines 368, 369,..., 370 whose time-delays run from 0 through (n - l).Tb2 in steps of Tb2. ;Consequently, bits output simultaneously by the delay lines 361, ..., 363 arrive with an increasing offset at the input of the additional delays lines 371, 372,..., 373, 15 374. They arc then spread out at intervals equal to the new bit period Tb2. The additional delay lines delay them uniformly by m.Tb2 to leave a gap between two successive cells for subsequent insertion of m routing label bits, m being equal to 24 in this example. At the output of the combiner 375 the various bits of the same ccll arrive serially with a bit period Tb2 appropriate to the required bit rate which is 2.6 20 Gb/s. ;The bit rate converter circuits D6. D7. D8 arc naturally of the same design as the circuit D5 described above. The bit rale converter circuits D1, D2, D3, D4 which change the bit rate from 2.6 Gb/s to 2.5 Gb/s arc of similar design with Tbl replaced by Tb2 for the delay lines 361, 362, ..., 363 and Tb2 replaced by Tbl for the delay 25 lines 368,..., 369, 370. On the other hand, the additional delay lines 371, 372,..., 373, 374 are not rcqurircd as there is no routing label to be inserted for the multiplexes ;45 ;24 14 0 2 ;MDl, MD2. The bit rate converter circuits D9 through Dl2 of the multiplexer/demultiplexer 4 arc identical to the circuit D5 described previously, the additonlal delay lines being retained with the same additional timc-dclay m.Tb2. The bit rate converter circuits D9 through DI2 are similar to the circuit D5 previously ;5 described except that the additional delay lines 371, 372, ..., 373, 374 are eliminated and the values Tbl and Tb2 arc interchanged. ;The multiplexer/demultiplexers 9. ctc. connccting the network 5 to a local central office are similar to the multiplexer/demultiplexers 3 and 4 dcscribcd above. ;The scope of the invention is not limited to the embodiments dcscribcd above. ;10 Numerous variants will be obvious to the man skilled in the art. In particular, it is possible to reorder the cclls addressed to subscriber terminal by means of a dedicated state on the input side of the stage 40 in cach concentrator interpreting two routing bits to change the order of the cclls and comprising a buffer with a capacity of at least four cells for each multiplex connecting a concentrator to the switching network. ;15 ;20 ;25 ;46 *<br><br></p> </div>

Claims (8)

<div class="application article clearfix printTableText" id="claims"> <p lang="en"> 241402<br><br> What we claim is:<br><br>

1. An optical subscriber access unit for connecting subscriber terminals sending and receiving data in the form of fixed length cells by asynchronous time-division multiplexing to a telecommunication network comprising:<br><br> - a switching network connected to a local central office;<br><br> - a control unit connected to the switching network;<br><br> - a plurality of concentrators connected to the switching network; and<br><br> - subscriber access circuits respectively connected to the subscriber terminals and to the concentrators;<br><br> said switching network, said control unit, said concentrators and said line terminals comprising:<br><br> - means for translating a virtual circuit label or virtual circuit group label included in each cell sent or received by the subscriber access unit and adding to it a routing label for routing said cell in said subscriber access unit;<br><br> -- means for synchronising each cell sent by a subscriber terminal with a local clock; and<br><br> -- means for implementing a policing function;<br><br> wherein the means for translating a virtual circuit label or virtual circuit group label for each cell sent or received by the subscriber access unit and adding a routing label to it are located in the switching network and are the same for processing the cells sent or received to or from all subscriber<br><br> /?\ si ■'* i' iv-..;terminals connected to at least one concentrator.;47;241402;

2. An optical subscriber access unit as claimed in claim 1, wherein said means for implementing the policing function are located in the switching network and the same policing means are used to process cells received from all the subscriber terminals connected to at least one concentrator.;

3. An optical subscriber access unit as claimed in claim 1, wherein said synchronisation means are located in each concentrator and each concentrator further comprises means for spectrally multiplexing cells received from subscriber terminals located on the input side of said synchronisation means.;

4. An optical subscriber access unit as claimed in claim 1, wherein each concentrator further comprises:;- means for multiplying the bit rate of the spectrally multiplexed and synchronised cells; and;- means for time-division multiplexing without spectral multiplexing the cells output by said bit rate multiplier means.;

5. An optical subscriber access unit as claimed in claim 1, wherein for sending cells to subscriber terminals each concentrator comprises means for spectrally demultiplexing cells.;

6. An optical subscriber access unit as claimed in claim 5, wherein for sending cells to subscriber terminals each concentrator further comprises:;- means for time-division demultiplexing cells supplied by said;^£N ?• •*..<br><br> switching network addressed to subscriber terminals;^ then s^jgfctrally<br><br> 48<br><br> 241402<br><br> multiplexing them; and<br><br> - means for dividing the bit rate of the cells supplied by said time-division demultiplexing and spectral multiplexing means, said divider means being located on the input side of said spectral demultiplexing means.<br><br>

7. An optical subscriber access unit as claimed in claim 6, wherein said means for time-division demultiplexing and spectral multiplexing cells supplied by said switching network addressed to subscriber terminals operate periodically and said switching network further comprises means for changing the order of the time-division multiplexed cells according to a routing label before they are supplied to a concentrator.<br><br>

8. An optical subscriber access unit substantially as herein described with reference to Figures 1 - 20 of the accompanying drawings.<br><br> P.M. Conrick Authorized Agent P5/1/1703<br><br> 49<br><br> </p> </div>