NL7601785A - Meer-cijferig rekenorgaan. - Google Patents
Meer-cijferig rekenorgaan.Info
- Publication number
- NL7601785A NL7601785A NL7601785A NL7601785A NL7601785A NL 7601785 A NL7601785 A NL 7601785A NL 7601785 A NL7601785 A NL 7601785A NL 7601785 A NL7601785 A NL 7601785A NL 7601785 A NL7601785 A NL 7601785A
- Authority
- NL
- Netherlands
- Prior art keywords
- calculator
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
- G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/386—Special constructional features
- G06F2207/3876—Alternation of true and inverted stages
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4924—Digit-parallel adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7601785A NL7601785A (nl) | 1976-02-23 | 1976-02-23 | Meer-cijferig rekenorgaan. |
DE2705989A DE2705989C2 (de) | 1976-02-23 | 1977-02-12 | Schaltungsanordnung zum parallelen Addieren oder Subtrahieren von mindestens zwei Eingangszahlen |
US05/769,414 US4139894A (en) | 1976-02-23 | 1977-02-17 | Multi-digit arithmetic logic circuit for fast parallel execution |
GB776895A GB1541961A (en) | 1976-02-23 | 1977-02-18 | Multi-digit arithmetic device |
FR7705032A FR2341896A1 (fr) | 1976-02-23 | 1977-02-22 | Organes de calcul a plusieurs chiffres |
JP1824977A JPS52116032A (en) | 1976-02-23 | 1977-02-23 | Parallel arithmetic unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7601785A NL7601785A (nl) | 1976-02-23 | 1976-02-23 | Meer-cijferig rekenorgaan. |
Publications (1)
Publication Number | Publication Date |
---|---|
NL7601785A true NL7601785A (nl) | 1977-08-25 |
Family
ID=19825662
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL7601785A NL7601785A (nl) | 1976-02-23 | 1976-02-23 | Meer-cijferig rekenorgaan. |
Country Status (6)
Country | Link |
---|---|
US (1) | US4139894A (de) |
JP (1) | JPS52116032A (de) |
DE (1) | DE2705989C2 (de) |
FR (1) | FR2341896A1 (de) |
GB (1) | GB1541961A (de) |
NL (1) | NL7601785A (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5892036A (ja) * | 1981-11-27 | 1983-06-01 | Toshiba Corp | 加算回路 |
US4638449A (en) * | 1983-06-15 | 1987-01-20 | International Business Machines Corporation | Multiplier architecture |
DE3323607A1 (de) * | 1983-06-30 | 1985-01-03 | Siemens AG, 1000 Berlin und 8000 München | Digitales rechenwerk |
US4644489A (en) * | 1984-02-10 | 1987-02-17 | Prime Computer, Inc. | Multi-format binary coded decimal processor with selective output formatting |
WO1986001017A1 (en) * | 1984-07-30 | 1986-02-13 | Arya Keerthi Kumarasena | The multi input fast adder |
JPS6149233A (ja) * | 1984-08-17 | 1986-03-11 | Nec Corp | 高速デジタル加減算回路 |
US5596763A (en) * | 1993-11-30 | 1997-01-21 | Texas Instruments Incorporated | Three input arithmetic logic unit forming mixed arithmetic and boolean combinations |
US7299254B2 (en) * | 2003-11-24 | 2007-11-20 | International Business Machines Corporation | Binary coded decimal addition |
US9258314B1 (en) * | 2013-03-15 | 2016-02-09 | Google Inc. | Detection of anomalous instances through dynamic feature selection analysis |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3100835A (en) * | 1960-01-06 | 1963-08-13 | Ibm | Selecting adder |
FR1390009A (fr) * | 1963-04-19 | 1965-02-19 | Philips Nv | Machine à calculer constituée principalement par une matrice-mémoire avec un appareillage accessoire |
US3316393A (en) * | 1965-03-25 | 1967-04-25 | Honeywell Inc | Conditional sum and/or carry adder |
US3553446A (en) * | 1966-08-04 | 1971-01-05 | Honeywell Inc | Carry determination logic |
DE1549530A1 (de) * | 1967-06-06 | 1971-03-04 | Siemens Ag | Schaltungsanordnung zum Addieren und Subtrahieren |
JPS5612898B2 (de) * | 1973-05-14 | 1981-03-25 | ||
JPS5047532A (de) * | 1973-08-27 | 1975-04-28 | ||
US3993891A (en) * | 1975-07-03 | 1976-11-23 | Burroughs Corporation | High speed parallel digital adder employing conditional and look-ahead approaches |
-
1976
- 1976-02-23 NL NL7601785A patent/NL7601785A/xx not_active Application Discontinuation
-
1977
- 1977-02-12 DE DE2705989A patent/DE2705989C2/de not_active Expired
- 1977-02-17 US US05/769,414 patent/US4139894A/en not_active Expired - Lifetime
- 1977-02-18 GB GB776895A patent/GB1541961A/en not_active Expired
- 1977-02-22 FR FR7705032A patent/FR2341896A1/fr active Granted
- 1977-02-23 JP JP1824977A patent/JPS52116032A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
US4139894A (en) | 1979-02-13 |
JPS52116032A (en) | 1977-09-29 |
DE2705989C2 (de) | 1986-09-11 |
FR2341896B1 (de) | 1983-09-23 |
DE2705989A1 (de) | 1977-08-25 |
FR2341896A1 (fr) | 1977-09-16 |
GB1541961A (en) | 1979-03-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
BV | The patent application has lapsed |