NL6411231A - - Google Patents
Info
- Publication number
- NL6411231A NL6411231A NL6411231A NL6411231A NL6411231A NL 6411231 A NL6411231 A NL 6411231A NL 6411231 A NL6411231 A NL 6411231A NL 6411231 A NL6411231 A NL 6411231A NL 6411231 A NL6411231 A NL 6411231A
- Authority
- NL
- Netherlands
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/4912—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/491—Indexing scheme relating to groups G06F7/491 - G06F7/4917
- G06F2207/49185—Using biquinary code, i.e. combination of 5-valued and 2-valued digits, having values 0, 1, 2, 3, 4 and 0, 5 or 0, 2, 4, 6, 8 and 0, 1 respectively
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4924—Digit-parallel adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Cash Registers Or Receiving Machines (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US312211A US3324288A (en) | 1963-09-27 | 1963-09-27 | Data processing apparatus including means for correcting codes arranged in a packed format |
Publications (1)
Publication Number | Publication Date |
---|---|
NL6411231A true NL6411231A (xx) | 1965-03-29 |
Family
ID=23210387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL6411231A NL6411231A (xx) | 1963-09-27 | 1964-09-25 |
Country Status (3)
Country | Link |
---|---|
US (1) | US3324288A (xx) |
GB (1) | GB1080642A (xx) |
NL (1) | NL6411231A (xx) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2479613A1 (fr) * | 1980-04-01 | 1981-10-02 | Cii Honeywell Bull | Procede de transformation de codes de caracteres numeriques recus ou fournis par un systeme de traitement de donnees et dispositif pour la mise en oeuvre de ce procede |
-
1963
- 1963-09-27 US US312211A patent/US3324288A/en not_active Expired - Lifetime
-
1964
- 1964-09-25 NL NL6411231A patent/NL6411231A/xx unknown
- 1964-09-25 GB GB39253/64A patent/GB1080642A/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
GB1080642A (en) | 1967-08-23 |
US3324288A (en) | 1967-06-06 |