NL2026434B1

NL2026434B1 - Input bias circuit for buffer amplifier

Info

Publication number: NL2026434B1
Application number: NL2026434A
Authority: NL
Inventors: Johannes Gerardus Bosch Jozef; Maria Lafort Adrianus
Original assignee: Sonion Nederland Bv
Priority date: 2020-09-09
Filing date: 2020-09-09
Publication date: 2022-05-09

Abstract

An input bias circuit comprising a first impedance cir— cuit (D1, D2) having a first impedance, said first impedance circuit (D1, D2) comprising a first and a second node, a second impedance circuit (D3, D4) having a second impedance, said sec— ond impedance circuit (D3, D4) comprising a first and a second node, wherein the first node is operatively connected to the second node of first impedance circuit (D1, D2). The first and second impedance circuits (D1, D2), (D3, D4) each comprises one or more semiconductor devices (D1, D2, D3, D4) characterised in that the first and second impedance circuits (D1, D2), (D3, D4) are connected in series, and in that the first and second imped— ance circuits (D1, D2), (D3, D4) each provides the characteris— tic of a pair of anti—parallel diodes.

Description

INPUT BIAS CIRCUIT FOR BUFFER AMPLIFIER

FIELD OF THE INVENTION The present invention relates to an input bias circuit adapted to increase the dynamic range for buffer amplifiers. In par- ticular, the present invention relates to an input bias cir- cuit comprising a first impedance circuit having a first im- pedance, said first impedance circuit comprising a first and a second node, and a second impedance circuit having a second impedance, said second impedance circuit comprising a first and a second node, wherein the first node is operatively con- nected to the second node of first impedance circuit, and wherein the first and second impedance circuits each comprises one or more semiconductor devices. The present invention fur- ther relates to an amplifier circuit and an acoustical assem- bly utilizing the input bias circuit.

BACKGOUND OF THE INVENTION It is widely accepted that the dynamics of an input voltage to a buffer amplifier should generally not exceed the power supply voltage range of the buffer amplifier in that this will introduce an undesired non-linearity/distortion of the output voltage of the buffer amplifier. In other words, the dynamics of an input voltage, i.e. the maximum voltage swing, is limited by the power supply voltage range of the buffer amplifier.

The above-mentioned limitation typically becomes crit- ical if the buffer amplifier is powered by a low-voltage power source, such as for example a battery having only a few volts (or even less than 1 V) between its battery terminals. Moreo- ver, 1f the source providing the input voltage to the buffer amplifier inherently generates an output voltage that exceeds the power supply voltage range of the buffer amplifier, the scenario becomes even more critical.

Within the hearing device industry scenarios involving low-voltage power sources (batteries) in combination with acoustical sensors, such as microphones, that inherently gen- erate higher output voltages, often arise. As mentioned above, this combination increases the risk of introducing an unde- sired non-linearity/distortion of the output voltage of the 40 buffer amplifier.

US 2018/0234762 Al relates to a microphone biasing circuit for increasing the so-called acoustical overload point of a microphone without introducing acoustical artifacts into the output signal. US 2018/0234762 Al discloses that single pairs of anti-parallel diodes may be applied at both the input of buffer amplifiers as well as in connection with biasing of microphones. However, the approach suggested in US 2018/0234762 Al does not solve the above-mentioned problem in that a single pair of anti-parallel diodes is not sufficient to avoid undesired non-linearity/distortion of the output voltage of the buffer amplifier at large input voltages. More- over, US 2018/0234762 Al is silent with respect to possible implementations of these diodes in a semiconductor device. It may be seen as an object of embodiments of the pre- sent invention to provide an input bias circuit for low volt- age applications that does not limit the linearity of, for ex- ample amplifiers at large input voltages.

DESCRIPTION OF THE INVENTION The above-mentioned object is complied with by provid- ing, in a first aspect, an input bias circuit comprising a) a first impedance circuit having a first impedance, said first impedance circuit comprising a first and a second node, b)a second impedance circuit having a second impedance, said second impedance circuit comprising a first and a second node, wherein the first node is operatively connected to the second node of first impedance circuit wherein the first and second impedance circuits each comprises one or more semiconductor devices, and wherein the first and second impedance circuits are connected in series, and wherein the first and second imped- ance circuits each provides the characteristic of a pair of anti-parallel diodes. The input bias circuit of the present invention is advantageous in that it, in connection with amplifier cir- cuits, allows that the input voltage levels can exceed the power supply voltage range of the amplifier with only limited distortion. This is particularly advantageous in relation to amplifier circuits being powered by a low supply voltage of 40 only a few volts (or even lower than 1V), such as a power voltage from a battery. Therefore, this could advantageously be applied in hearing devices, such as hearing aids/hearables, earbuds and the like, where the input voltage from, for exam- ple, a MEMS cartridge often exceeds the power supply voltage level of the amplifier.

Thus, according to the first aspect of the present in- vention, an impedance circuit in the form of an input bias circuit is provided. As it will become apparent from the fol- lowing description, the input bias circuit may be used in var- ious applications, such as in connection with low voltage am- plifiers and charged pumps for MEMS microphones.

As mentioned above, the first and second impedance circuits each provides the characteristic of a pair of anti- parallel diodes. In the present context this should be taken to mean that the behaviour of each of the first and second im- pedance circuits is defined only by a pair of anti-parallel diodes, i.e. without the influence of parasitic diodes. As it will be demonstrated in the following this may be achieved by implementing the anti-parallel diodes in such a way that unde- sired parasitic diodes are either shorted, reversed biased or by other means made harmless.

The one or more semiconductor devices may be either controllable or passive semiconductor devices or even a combi- nation thereof. The first and second impedance circuits may thus each comprise a pair of p-channel MOSFETs. The p-channel MOSFETs are controlled in such a manner that the first and second impedance circuits each provides the characteristic of a pair of anti-parallel diodes without parasitic diodes. Al- ternatively, and preferably, the first and second impedance circuits each comprises a pair of anti-parallel diodes imple- mented in a stacked arrangement on top of a p-type substrate in order to avoid parasitic diodes.

In a second aspect, the present invention relates to an amplifier circuit configured to receive an input voltage and provide an output voltage, wherein the amplifying circuit comprises an input bias circuit according to the first aspect, and a buffer amplifier having an input and an output, wherein the first node of the input bias circuit is operatively con- nected to the input of the amplifier.

Thus, according to the second aspect, an amplifier circuit comprising an input bias circuit is provided. As al- ready addressed, the role of the input bias circuit is to fa- cilitate that the input voltage level to the amplifier may ex- ceed the power supply voltage range of the amplifier with only limited distortion. This is advantageous in relation to an am- plifier being powered by a battery having only a few volts be- tween its battery terminals. The amplifier circuit of the sec- ond aspect may advantageously be applied in hearing devices, such as hearing aids/hearables, earbuds and the like, where the input voltage from, for example, a MEMS cartridge often exceeds the power supply voltage level of the amplifier.

In terms of implementation, the second node of the first impedance circuit is preferably operatively connected to the output of the amplifier via a first DC blocking capaci- tance. The second node of the second impedance circuit is preferably operatively connected to a predetermined potential, such as ground. The dimensioning of the first and second im- pedances, the first DC blocking capacitance and an input ca- pacitance of the amplifier is discussed in relation to the ap- pended figures.

In order to facilitate that the input voltage levels to the amplifier may exceed the power supply voltage range of the amplifier with only limited distortion the characteristic of the pairs of anti-parallel diodes of the first and second impedance circuits may not be influenced by undesired para- sitic diodes.

To avoid the influence of parasitic diodes the pair of anti-parallel diodes of the first impedance circuit preferably comprises a first diode and a second diode, where the first diode is implemented across a junction between an n-type dif- fusion and a p-type well, and wherein the second diode is im- plemented across a junction between a p-type diffusion and an n-type well. Similarly, the pair of anti-parallel diodes of the second impedance circuit preferably comprises a first di- ode and a second diode, where the first diode is implemented across a junction between the n-type well and the p-type sub- strate, and wherein the second diode is implemented across a junction between the p-type well and a deep n-type well.

In order to avoid parasitic diodes each pair of anti- parallel diodes is preferably arranged on one or more oxide structures being arranged on the p-type substrate. In this way the diodes are electrically isolated from the substrate. In an 5 alternative implementation, the diodes forming the pairs of the anti-parallel diodes are preferably defined as laterally arranged diodes on top of an oxide structure in order to avoid parasitic diodes, wherein the I-V characteristic of the re- spective diodes is defined by a width of a salicide blocking region between a p-type polysilicon structure and an n-type polysilicon structure.

In a second embodiment, the second node of the second impedance circuit is preferably operatively connected to the output of the amplifier via a second DC blocking capacitance.

Moreover, the amplifier circuit preferably further comprises a third impedance circuit having a third impedance, said third impedance circuit comprising a first and a second node, wherein the first node is operatively connected to the second node of second impedance circuit, and wherein the third imped- ance circuit comprises a pair of anti-parallel diodes imple- mented in a stacked arrangement on top of a p-type substrate in order to avoid parasitic diodes. The second node of the third impedance circuit is preferably operatively connected to a predetermined potential, such as ground. The third impedance circuit is thus preferably connected in series with the first and second impedance circuits.

In a third aspect the present invention relates to an acoustical assembly comprising a transducer and an amplifier circuit according to the second aspect, wherein an output voltage from the transducer is provided as an input voltage to the amplifier circuit. Preferably the amplifier circuit has an input capacitance.

The transducer may in principle be any type of trans- ducer or sensor capable of generating an output voltage in re- sponse to a measured parameter. Preferably, the transducer is a pressure sensor, such as a MEMS microphone having a MEMS ca- pacitance. The microphone may be an electret microphone or a MEMS microphone having a biased/charged pumped membrane. The acoustical assembly of the third aspect may advantageously be applied in hearing devices, such as hearing aids, hearables, earbuds or the like.

In terms of dimensional and thus optimising the per- formance of the acoustical assembly the capacitances of the assembly, i.e. the DC blocking capacitance, the MEMS capaci- tance and the input capacitance of the amplifier circuit should be properly selected. Thus, in case the second node of the first impedance circuit is operatively connected to the output of the amplifier via a first DC blocking capacitance, sald first DC blocking capacitance should preferably be smaller or equal to a sum of the MEMS capacitance and the in- put capacitance of the amplifier circuit. Moreover, and in case the second node of the first impedance circuit is opera- tively connected to the output of the amplifier via a first DC blocking capacitance, a time constant set by said first DC blocking capacitance in combination with the second impedance circuit should preferably be smaller than a time constant set by a sum of the MEMS capacitance and the input capacitance of the amplifier circuit in combination with the first impedance circuit. The performance of the acoustical assembly is dis- cussed in further details below.

In case the MEMS microphone has a biased/charged pumped membrane the acoustical assembly preferably further comprises a charge pump arrangement for providing charges to the MEMS capacitance of the MEMS microphone, the charge pump arrangement comprising a) a charge pump having an output, b) a first impedance circuit having a first impedance, said first impedance circuit comprising a first and a second node, wherein the first node is operatively connected to the MEMS microphone, and c) a second impedance circuit having a second impedance, said second impedance circuit comprising a first and a second node, wherein the first node is operatively con- nected to the second node of first impedance circuit, and wherein the second node is operatively connected to the output of the charge pump wherein the first and second impedance circuits are connected in series, and wherein the first and second imped- 40 ance circuits each comprises one or more semiconductor devices, and wherein the first and second impedance circuits each provides the characteristic of a pair of anti-parallel diodes.

Again, the behaviour of each of the first and second 5 impedance circuits is defined only by a pair of anti-parallel diodes, i.e. without the influence of parasitic diodes.

As it will be demonstrated below this may be achieved by implement- ing the anti-parallel diodes in such a way that undesired par- asitic diodes are either shorted, reversed biased or by other means made harmless.

The one or more semiconductor devices may again be ei- ther controllable or passive semiconductor devices or even a combination thereof.

The first and second impedance circuits of the charge pump arrangement may thus each comprise a pair of p-channel MOSFETs.

The p-channel MOSFETs are controlled in such a manner that the first and second impedance circuits of the charge pump arrangement each provides the characteristic of a pair of anti-parallel diodes without parasitic diodes.

Alternatively, and preferably, the first and second impedance circuits of the charge pump arrangement each comprises a pair of anti-parallel diodes implemented in a stacked arrangement on top of a p-type substrate in order to avoid parasitic di- odes.

Preferably, the first and second impedance circuits of the charge pump arrangement are bootstrapped in that the sec- ond node of the first impedance circuit of the charge pump ar- rangement is operatively connected to the output of the ampli- fier via a first DC blocking capacitance.

The charge pump ar- rangement preferably further comprises a second DC blocking capacitance inserted between the input of the amplifier and the first node of the first impedance circuit of the charge pump arrangement.

In terms of implementation the first impedance circuit charge pump arrangement preferably comprises a pair of anti- parallel diodes comprising a first diode and a second diode, where the first diode is implemented across a junction between a p-type diffusion and an n-type deep well, and wherein the second diode is implemented across a junction between a p-type well and an n-type diffusion.

Similarly, the second impedance 40 circuit charge pump arrangement preferably comprises a pair of anti-parallel diodes comprising a first diode and a second di- ode, where the first diode is implemented across a junction between p-type diffusion and an n-type deep well, and wherein the second diode is implemented across a junction between the p-type well and an n-type diffusion.

In a fourth aspect the present invention relates to a hearing device comprising an acoustical assembly according to the third aspect. Preferably, the hearing device is a hearing aid, a hearable, an earbud or the like.

In general, the various aspects of the invention may be combined and coupled in any way possible within the scope of the invention. These and other aspects, features and/or ad- vantages of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be described in further details with reference to the accompanying figures where Fig. 1 shows an amplifier that receives an input volt- age having a dynamic range larger than the power supply volt- age level of the amplifier, Fig. 2 shows an input bias circuit at the input of an amplifier, and an implementation of a pair of anti-parallel diodes using p-channel MOSFETs, Fig. 3 shows an input bias circuit at the input of an amplifier, the input bias circuit comprising two pairs of anti-parallel diodes, Fig. 4 shows an input bias circuit at the input of an amplifier, the input bias circuit comprising three pairs of anti-parallel diodes, Fig. 5 shows an input bias circuits at the input of an amplifier and between a membrane of a MEMS microphone and a bias voltage source, the input bias circuits each comprises two pairs of anti-parallel diodes, Fig. 6 shows a cross-sectional view of symmetrical vertical crosswise diode structures without parasitic diodes, Fig. 7 shows input bias circuits in a feedback config- uration and a cascaded configuration using diodes D1-D4 of Fig. 6, Fig. 8 shows a cross-sectional view of diode struc- 40 tures isolated on a (field) oxide layer,

Fig. 9 shows a schematic cross-sectional view of a pol- ysilicon diode in a standard bulk CMOS process, and Fig. 10 shows floating symmetrical dicde structures with- out parasitic diodes in the signal path.

DETAILED DESCRIPTION OF THE INVENTION As already mentioned, the present invention relates to an in- put bias circuit comprising a first impedance circuit having a first impedance, and a second impedance circuit having a sec- ond impedance, wherein the first and second impedance circuits each provides the characteristic of a pair of anti-parallel diodes without parasitic diodes. The input bias circuit of the present invention may be used in various applications, such as at the input node of an amplifier circuit and/or in connection with charge pumps for MEMS cartridges.

In relation to amplifier circuits, reference is now made to Fig. 1 which shows an amplifier 102 that receives an input voltage 103 from a MEMS cartridge 101. The MEMS car- tridge 101 may be an electret cartridge or a biased/charged pumped MEMS cartridge. As seen in Fig. 1 the linear range of the input voltage 103 from the MEMS cartridge 101 exceeds the power supply voltage level (Vdd) of the amplifier 102 and thus also exceeds the maximum output voltage range 104 of the am- plifier 102. As a consequence the linearity of the amplifier 102 becomes limited, and distortion and other undesired arte- facts may be introduced due to conducting parasitic diodes as discussed thoroughly below.

Turning now to Fig. 2a, a simplified electrical dia- phragm of a buffer amplifier connected to a MEMS cartridge is depicted. As seen in Fig. Za, the buffer amplifier has a gain G (close to unity) and an input capacitance C in. An impedance circuit comprising a pair of anti-parallel diodes Dl, D2 is connected to the input of the buffer amplifier via a first/up- per node, whereas the second/lower node of the anti-parallel diodes Dl, D2 is connected to the output of the buffer ampli- fier via a DC blocking capacitance C b, i.e. the anti-parallel diodes D1, D2 are bootstrapped. Moreover, a bias impedance Z b is connected to the second/lower node of the anti-parallel di- odes D1, D2 as well as to ground. The power supply to the buffer amplifier is not shown. The MEMS cartridge comprises 40 biased MEMS backplate BP which forms a MEMS capacitance C MEMS with the membrane D of the MEMS cartridge. A voltage source V bias biases the backplate BP. For input signal frequencies above the cut-off frequency defined by the product of the DC blocking capacitance C b and the bias impedance Z b, i.e. Cb x Z b, the voltage across the anti-parallel diodes Dl, D2 is kept close to zero by the buffer amplifier thus ensuring the desired high input impedance.

When designing the bias impedance Z b relative to the DC blocking capacitance C b it should be noted that Z b should be high enough to follow the output voltage Vout of the buffer amplifier, and it should, at the same time, be low enough to ensure fast settling of the input voltage Vin to the buffer amplifier. Moreover, both the bias impedance Z b and the DC blocking capacitance C b should preferably be able to be manu- factured using standard ASIC manufacturing processes without using disproportionately large areas.

With reference to Fig. 2b, the pair of anti-parallel diodes D1, D2 may be implemented using either controllable or passive semiconductor devices. The anti-parallel diodes D1, D2 may thus be implemented using a pair of p-channel MOSFETs MI, M2. The p-channel MOSFETs Ml, MZ are controlled in such a man- ner that they provide the characteristic of a pair of anti- parallel diodes without parasitic diodes. Preferably, the pair of anti-parallel diodes Dl, D2 are implemented as passive di- odes in a stacked arrangement on top of a p-type substrate in order to avoid parasitic diodes.

Referring now to Fig. 3 the bias impedance Z b of Fig. 2a has been replaced by a pair of anti-parallel diodes D3, D4 having a first/upper node connected to the second/lower node of the anti-parallel diodes Dl, D2. The remaining circuit to- pology is the same as depicted in Fig. 2.

In order to ensure fast settling of the bootstrapped diodes, the settling time of the combination C b (DC blocking capaci- tance) with anti-parallel diodes D3, D4 should be similar or faster than the settling time of the combination C MEMS + C in (MEMS capacitance + input capacitance) with anti-parallel di- odes Dl, D2. This may be achieved in one of the following two ways: 1) using identical diodes and choosing C b = (C MEMS + 40 C in), or

2) using C b = (C MEMS + C in) and choosing larger satura- tion current for anti-parallel diodes D3, D4 than for anti-parallel diodes Dl, D2 Option 1 may have an effect on the bootstrapping. Op- tion 2 is the preferred solution because the settling of the voltage on the first/upper node of diode pair D3, D4 is less affected by the voltage on the first/upper node of diode pair D1, D2 compared with option 1. If the buffer amplifier should be capable of handling even larger input voltages with even larger voltage swings, an additional pair of anti-parallel diodes D5, D6 and an addi- tional DC blocking capacitance C b2 may advantageously be added, cf. Fig. 4. The DC blocking capacitance C bl in Fig. 4 is identical with the DC blocking capacitance C b in Figs. 2 and 3. As seen in Fig. 4 the pair of anti-parallel diodes D5, D6 has a first/upper node connected to the second/lower node of the anti-parallel diodes D3, D4 to which the additional DC blocking capacitance C bZ is also connected. The additional DC blocking capacitance C b2 is also connected to the output of the buffer amplifier. It should be noted that even further pairs of anti-parallel diodes an additional DC blocking capac- itances may be added.

Turning now to Fig. 5, the backplate BP of the MEMS cartridge is now connected to ground, and the membrane D of the MEMS cartridge is biased by the voltage source V bias through two pairs of anti-parallel diodes D7, D8 and DS, D10. As seen in Fig. 5 a first/upper node of the pair of anti-par- allel diodes D7, D8 is connected to the membrane D of the MEMS cartridge, whereas a second/lower node of the pair of anti- parallel diodes D7, D8 is connected to a first/upper node of the pair of anti-parallel diodes D8, D10. A DC blocking capac- itance C b2 is inserted between the first/upper node of the pair of anti-parallel diodes D9, D10 and the output of the buffer amplifier. Finally, a DC blocking capacitance C k is inserted between the first/upper node of the pair of anti-par- allel diodes D7, D8 and the input of the buffer amplifier. The role of the two pairs of anti-parallel diodes D7, D8 and D9, D10 is to provide high impedance circuit using a very limited space.

In Figs. 6-10 various implementations of the pairs of anti-parallel diodes will be depicted and discussed. The over- all aim of the implementation of the pairs of anti-parallel diodes is that they should be capable of handling large input voltages without distortion. In order to achieve this, the large signal behaviour should only be determined by the pairs of anti-parallel diodes - and not by parasitic diodes and/or signal switches. This means that the parasitic diodes should either be absent (which is preferred), or alternatively, the parasitic diodes should only conduct at even larger signal voltages than the rated operating voltages of the anti-paral- lel diodes. Moreover, in case parasitic diodes cannot be avoided, they should conduct in a symmetric way.

Referring now to Fig. 6, an exemplary embodiment of the implementation of the pairs of anti-parallel diodes D1-D4 is depicted in a cross-sectional view. Suitable applications of the anti-parallel diodes D1-D4 are depicted in Fig. 7 in the form of input bias circuits for buffer amplifiers 702 (with or without feedback}. The input bias circuits comprise first and second impedance circuits comprising anti-parallel diodes Dl, D2 and D3, D4. As depicted in Fig. 7 the buffer am- plifiers 702 are connected to MEMS cartridges 701. In the up- per circuit a DC blocking capacitance 703 is inserted between the output of the amplifier 702 and a middle node between the pairs of anti-parallel diodes D1, D2 and D3, D4.

Referring again to Fig. 6, an implementation involving symmetrical vertical crosswise diode structures without para- sitic diodes is depicted. The implementation depicted in Fig. 6 is manufactured using standard CMOS processes. As shown in Fig. 6 the combination of stacked diode pairs and single-ended grounding facilitates that it is possible to implement the anti-parallel diodes D1-D4 vertically on top of the p-type substrate. Connecting each pairs of anti-parallel diodes to- gether enables crosswise implementation in the vertical struc- ture. The only parasitic diode left in this embodiment is shorted, and thus harmless, as indicated by the crossed out diode.

Still referring to Fig. 6 the pair of anti-parallel diodes D1, D2 of a first impedance circuit comprise a first 40 diode D1 and a second diode D2, where the first diode Dl is implemented across a junction between an n-type diffusion and a p-type well, and wherein the second diode D2 is implemented across a junction between a p-type diffusion and an n-type well. Similarly, the pair of anti-parallel diodes of a second impedance circuit comprise a first diode D3 and a second diode D4, where the first diode D3 is implemented across a junction between the n-type well and the p-type substrate, and wherein the second diode D4 is implemented across a junction between the p-type well and a deep n-type well. The connections “in- put” and “feedback” in Fig. 6 correspond to circuit points 704 and 705 in Fig. 7, respectively.

By applying the stacked diodes D1-D4 in an input cir- cuit as depicted in Fig. 7, the input voltage behaviour is de- termined only by these diodes D1-D4 for all voltage levels.

Moreover, the input voltage behaviour can be designed to be completely symmetrical. These advantages lead to less and bet- ter predictable voltage behaviour in relation to distortion and artefacts.

In another exemplary embodiment isolated diodes are implemented on top of a local thick oxide. With this implemen- tation parasitic diodes are also avoided. The diodes may, as shown in Fig. 8, share a local thick oxide, or they may be im- plemented on top of their own thick field oxide (not shown). The exemplary embodiment shown in Fig. 8 is advantageous due to its similarity to oxide isolated poly-poly capacitors of- fered in standard CMOS processes where the capacitator dielec- tric oxide between the two poly-layers (N-poly and P-poly} is absent. Two possible implementations are shown in Fig. 8, one diode where the lower poly layer is a p-type and the upper poly layer is an n-type (diode to the left), and another diode where the lower poly layer is an n-type and the upper poly layer is a p-type (diode in the middle). The structure to the right in Fig. 8 is a poly-poly capacitor with a dielectric ox- ide.

In yet another exemplary embodiment, as shown in Fig. 9, isolated and laterally arranged poly-silicon diodes are built on a top oxide layer using standard CMOS processes in order to avoid parasitic diodes. Optionally, a shallow trench isolation layer {STI-layer) may be provided as well. The iso- 40 lated and laterally arranged poly-silicon diodes can be electrically stacked, made symmetric and their I-V character- istics can be adjusted with the length of the un-doped centre region (Lc). Thus, the I-V characteristic of the respective poly-silicon diodes is defined by the width of the ilicide blocking region between the p-type polysilicon structure P to the left and an n-type polysilicon structure N to the right.

In alternative exemplary embodiments of the present invention isolated diodes may be arranged on a silicon on in- sulator (SOI) substrate.

In even further alternative exemplary embodiments of the present invention, diode and/or signal switching structures may be implemented using standard CMOS processes, e.g. isolated NMOS.

In this approach parasitic di- odes may be present, but they are 1) completely symmetrical and they 2) only conduct at larger voltage levels compared to the voltage levels being handled by the stacked pairs of anti- parallel diodes.

In yet another exemplary embodiment of the present in- vention, electrically floating symmetrical diode structures DS, D10, D7, D8 without parasitic diode are arranged in the signal path between a charge pump and a MEMS cartridge, cf.

Fig. 10b.

The MEMS cartridge, an input bias circuit comprising two pairs of anti-parallel diodes and a DC blocking capaci- tance connected thereto {and to the output of the ampli- fier/transistor) are depicted by dotted lines in Fig. 10b as focus in this exemplary embodiment is on the anti-parallel di- odes D9, D10, D7, D8 operatively connected to the change pump.

The role of the charge pump is to bias the membrane of the MEMS cartridge via the two pairs of anti-parallel diodes D9, D10 and D7, D8. The backplate of the MEMS cartridge is grounded.

This exemplary embodiment can be built using stand- ard CMOS processes.

Preferably, the characteristic of D9 equals the characteristic of D10, and the characteristic of D7 equals the characteristic of D8. Still referring to Fig. 10b a first impedance circuit comprising anti-parallel diodes D7, D8 is provided.

The first impedance circuit has a first impedance and comprises a first and a second node, wherein the first node is operatively con- nected to the membrane of the MEMS cartridge.

A second imped- ance circuit comprising anti-parallel diodes D9, D10 is con- 40 nected in series with the first impedance circuit comprising anti-parallel diodes D7, D8. The second impedance circuit has second impedance and comprises a first and a second node, wherein the first node is operatively connected to the second node of first impedance circuit, and wherein the second node is operatively connected to the output of the charge pump. As seen in Fig. 10b the second node of the first impedance cir- cuit comprising anti-parallel diodes D7, D8 is operatively connected to the output of the amplifier/transistor via a ca- pacitor in the form of a DC blocking capacitance C b2. It should however be noted that the DC blocking capacitance C b2 is optional. Moreover, a first diode D11 is inserted between second node of the first impedance circuit and ground, and a second diode D12 is inserted between the charge pump output and ground.

In terms of implementation reference is now made to Fig. 10a where the first impedance circuit comprises the pair of anti-parallel diodes comprising the first diode D7 and the second diode D8, where the first diode D7is implemented across a junction between a p-type well and an n-type diffusion, and wherein the second diode D8 is implemented across a junction between a p-type diffusion and an n-type deep well. Similarly, the second impedance circuit comprises the pair of anti-paral- lel diodes D9, D10 comprising the first diode D9 and the sec- ond diode D10, where the first diode DS is implemented across a junction between p-type diffusion and an n-type deep well, and wherein the second diode D10 is implemented across a junc- tion between the p-type well and an n-type diffusion. The first and second impedance circuits are arranged on top of a p-type substrate. The first diode D11 (inserted between second node of the first impedance circuit and ground, cf. Fig. 10b) is implemented across a junction between the p-type substrate and the n-type deep well. The second diode D12 (inserted be- tween the charge pump output and ground, cf. Fig. 10b) is im- plemented in a similar manner. The two parasitic diodes left in this embodiment are reversed biased, and thus harmless, as indicated by the crossed out diodes.

Although the invention has been discussed in the foregoing with reference to exemplary embodiments of the in- vention, the invention is not restricted to these particular 40 embodiments which can be varied in many ways without departing from the invention. The discussed exemplary embodiments shall therefore not be used to construe the appended claims strictly in accordance therewith. On the contrary, the embodiments are merely intended to explain the wording of the appended claims, without intent to limit the claims to these exemplary embodi- ments. The scope of protection of the invention shall there- fore be construed in accordance with the appended claims only, wherein a possible ambiguity in the wording of the claims shall be resolved using these exemplary embodiments. Aspects of the invention are itemized in the follow- ing section.

1. An input bias circuit comprising a) a first impedance circuit (Dl, D2) having a first imped- ance, said first impedance circuit (D1, D2) comprising a first and a second node, b) a second impedance circuit (D3, D4) having a second im- pedance, said second impedance circuit (D3, D4) compris- ing a first and a second node, wherein the first node is operatively connected to the second node of first imped- ance circuit (D1, D2) wherein the first and second impedance circuits (Dl, D2), (D3, D4) each comprises one or more semiconductor devices (D1, D2, D3, D4) characterised in that the first and second impedance circuits (Dl, DZ), (D3, D4) are connected in series, and in that the first and second impedance circuits (D1, D2), (D3, D4) each provides the characteristic of a pair of anti- parallel diodes.

2. An input bias circuit according to claim 1, charac- terised in that the first and second impedance circuits (Dl, D2), (D3, D4) each comprises a pair of anti-parallel diodes implemented in a stacked arrangement on top of a p-type sub- strate in order to avoid parasitic diodes.

3. An amplifier circuit configured to receive an input voltage and provide an output voltage characterised in that the amplifying circuit comprises an input bias circuit accord- ing to any of the preceding claims, and an amplifier (G) hav- ing an input and an output, wherein the first node of the in- put bias circuit is operatively connected to the input of the amplifier {G&G}.

4, An amplifier circuit according to claim 3, charac- terised in that the second node of the first impedance circuit (D1, D2) is operatively connected to the output of the ampli- fier via a first DC blocking capacitance (C b).

5. An amplifier circuit according to claim 3 or 4, characterised in that the second node of the second impedance circuit (D3, D4) is operatively connected to a predetermined potential, such as ground.

6. An amplifier circuit according to any of claims 3- 5, characterised in that the pair of anti-parallel diodes of the first impedance circuit comprises a first diode (Dl) and a second diode (D2), where the first diode (Dl) is implemented across a junction between an n-type diffusion and a p-type well, and wherein the second diode (D2) is implemented across a junction between a p-type diffusion and an n-type well, and in that the pair of anti-parallel diodes of the second imped- ance circuit comprises a first diode (D3) and a second diode (D4), where the first diode (D3) is implemented across a junc- tion between the n-type well and the p-type substrate, and wherein the second diode (D4) is implemented across a junction between the p-type well and a deep n-type well.

7. An amplifier circuit according to any of claims 3- 5, characterised in that each pair of anti-parallel diodes are arranged on one or more oxide structures in order to avoid parasitic diodes, the one or more oxide structures being ar- ranged on the p-type substrate.

8. An amplifier circuit according to any of claims 3- 5, characterised in that the diodes forming the pairs of the anti-parallel diodes are defined as laterally arranged diodes on top of a oxide structure in order to avoid parasitic di- odes, wherein the I-V characteristic of the respective diodes is defined by a width of a salicide blocking region between a p-type polysilicon structure and an n-type polysilicon struc- ture.

9. An acoustical assembly comprising a transducer and an amplifier circuit according to any of claims 3-8, wherein an output voltage from the transducer is provided as an input voltage to the amplifier circuit.

10. An acoustical assembly according to claim 9, char- 40 acterised in that the amplifier circuit has an input capacitance (C in), and in that the transducer is a MEMS mi- crophone having a MEMS capacitance (C MEMS).

11. An acoustical assembly according to claim 10, characterised in that, in case the second node of the first impedance circuit (Dl, D2) is operatively connected to the output of the amplifier via a first DC blocking capacitance (Cb), said first DC blocking capacitance (C b) is smaller or equal to a sum of the MEMS capacitance (C MEMS) and the input capacitance (C in) of the amplifier circuit.

12. An acoustical assembly according to claim 10, characterised in that, in case the second node of the first impedance circuit (Dl, DZ) is operatively connected to the output of the amplifier via a first DC blocking capacitance (Cb), a time constant set by said first DC blocking capaci- tance (C b) in combination with the second impedance circuit (D3, D4) is smaller than a time constant set by a sum of the MEMS capacitance (C MEMS) and the input capacitance (C in) of the amplifier circuit in combination with the first impedance circuit (Dl, D2).

13. An acoustical assembly according to any of claims 10-12, characterised in that the acoustical assembly further comprising a charge pump arrangement for providing charges to the MEMS capacitance of the MEMS microphone, the charge pump arrangement comprising a) a charge pump (V bias) having an output, b) a first impedance circuit (D7, D8) having a first imped- ance, said first impedance circuit (D7, D8) comprising a first and a second node, wherein the first node is opera- tively connected to the MEMS microphone, and c) a second impedance circuit (D9, D10) having a second im- pedance, said second impedance circuit (D9, D10) compris- ing a first and a second node, wherein the first node is operatively connected to the second node of first imped- ance circuit (D7, D8), and wherein the second node is op- eratively connected to the output of the charge pump (V bias). wherein the first and second impedance circuits (D7, D8), (D9, D10}) are connected in series, and wherein the first and second impedance circuits (D7, D8), (DS, D10) each com- 40 prises one or more semiconductor devices (D7, D8, D9, D10},

and wherein the first and second impedance circuits (D7, D8), (D9, D10) each provides the characteristic of a pair of anti- parallel diodes.

14. An acoustical assembly according to claim 13, characterised in that the first and second impedance circuits (D7, D8), (D9, D10) each comprises a pair of anti-parallel di- odes implemented in a stacked arrangement on top of a p-type substrate in order to avoid parasitic diodes.

15. A hearing device, such as a hearing aid, a heara- ble or an earbud, characterised in that the hearing device comprises an acoustical assembly according to any of claims 9-

14.

Claims

CONCLUSIESCONCLUSIONS

1. Een ingangs-instelschakeling omvattende a) een eerste impedantieschakeling (D1, D2) met een eerste impedantie, de eerste impedantieschakeling (D1, D2) om- vattende een eerste en een tweede knooppunt, b) een tweede impedantieschakeling (D3, D4) met een tweede impedantie, de tweede impedantieschakeling (D3, D4) om- vattende een eerste en een tweede knooppunt, waarbij het eerste knooppunt werkend verbonden is met het tweede knooppunt van de eerste impedantieschakeling {Dl, D2}, waarbij de eerste en tweede impedantieschakelingen (D1, D2), (D3, D4) elk één of meer halfgeleiderelementen (Dl, D2, D3, D4) omvatten met het kenmerk, dat de eerste en tweede impedantieschakelingen (D1, D2), (D3, D4) in serie zijn verbonden, en dat de eerste en tweede impedantieschakelingen (Dl, D2), (D3, D4) elk de karakteristiek van een paar anti-pa- rallelle diodes verschaffen.An input bias circuit comprising a) a first impedance circuit (D1, D2) having a first impedance, the first impedance circuit (D1, D2) including a first and a second node, b) a second impedance circuit (D3, D4) having a second impedance, the second impedance circuit (D3, D4) comprising a first and a second node, the first node operatively connected to the second node of the first impedance circuit {D1, D2}, the first and second impedance circuits (D1, D2), (D3, D4) each comprise one or more semiconductor elements (D1, D2, D3, D4) characterized in that the first and second impedance circuits (D1, D2), (D3, D4) are in series connected, and that the first and second impedance circuits (D1, D2), (D3, D4) each provide the characteristic of a pair of anti-parallel diodes.

2. Een ingangs-instelschakeling volgens conclusie 1 met het kenmerk, dat de eerste en tweede impedantieschakelin- gen (D1, D2), (D3, D4) elk een paar anti-parallelle diodes omvatten in een gestapelde opstelling bovenop een p-type sub- straat om parasitaire diodes te vermijden.An input bias circuit according to claim 1, characterized in that the first and second impedance circuits (D1, D2), (D3, D4) each comprise a pair of anti-parallel diodes in a stacked arrangement on top of a p-type sub - street to avoid parasitic diodes.

3. Een versterkerschakeling ingericht om een ingangs- voltage te ontvangen en een uitgangsvoltage te verschaffen met het kenmerk, dat de versterkerschakeling een ingangs-instel- schakeling omvat volgens één van de voorgaande conclusies, en een versterker (G) met een ingang en een uitgang, waarbij het eerste knooppunt van de ingangs-instelschakeling werkend is verbonden met de ingang van de versterker (G).An amplifier circuit arranged to receive an input voltage and provide an output voltage, characterized in that the amplifier circuit comprises an input bias circuit according to any one of the preceding claims, and an amplifier (G) having an input and an output wherein the first node of the input bias circuit is operably connected to the input of the amplifier (G).

4. Een versterkerschakeling volgens conclusie 3 met het kenmerk, dat het tweede knooppunt van de eerste impedan- tieschakeling (D1, D2) werkend verbonden is met de uitgang van de versterker via een eerste wisselstroom koppelcondensator (Cb).An amplifier circuit according to claim 3, characterized in that the second node of the first impedance circuit (D1, D2) is operably connected to the output of the amplifier via a first alternating current coupling capacitor (Cb).

5. Een versterkerschakeling volgens conclusie 3 of 4 met het kenmerk, dat het tweede knooppunt van de tweede impe- dantieschakeling (D3, D4) werkend verbonden is met een vooraf gedefinieërde potentiaal, zoals aarde.An amplifier circuit according to claim 3 or 4, characterized in that the second node of the second impedance circuit (D3, D4) is operably connected to a predefined potential, such as ground.

6. Een versterkerschakeling volgens één van de conclusies 3-5 met het kenmerk, dat het paar anti-parallelle diodes van de eerste impedantieschakeling een eerste diode (D1) en een tweede diode (D2) omvat, waarbij de eerste diode (D1) gerealiseerd is als een overgang tussen een n-type diffusie en een p-type well, en waarbij de tweede diode (D2) gerealiseerd is als een overgang tussen een p-type diffusie en een n-type well en dat het paar anti-parallelle diodes van de tweede impedantieschakeling een eerste diode (D3) en een tweede diode (D4) omvat, waarbij de eerste diode (D3) gerealiseerd is als een overgang tussen een n-type well en het p-type substraat, en waarbij de tweede diode (D4) gerealiseerd is als een overgang tussen de p-type well en een diepe n-type well.An amplifier circuit according to any one of claims 3 to 5, characterized in that the pair of anti-parallel diodes of the first impedance circuit comprises a first diode (D1) and a second diode (D2), the first diode (D1) being realized is as a transition between an n-type diffusion and a p-type well, and where the second diode (D2) is realized as a transition between a p-type diffusion and an n-type well and that the pair of anti-parallel diodes of the second impedance circuit comprises a first diode (D3) and a second diode (D4), the first diode (D3) being realized as a junction between an n-type well and the p-type substrate, and the second diode ( D4) is realized as a transition between the p-type well and a deep n-type well.

7. Een versterkerschakeling volgens één van de conclu- sies 3-5 met het kenmerk, dat elk paar anti-parallelle diodes is aangebracht op één of meer oxide structuren om parasitaire diodes te vermijden, waarbij de één of meer oxide structuren zijn aangebracht op het p-type substraat.An amplifier circuit according to any one of claims 3 to 5, characterized in that each pair of anti-parallel diodes is provided on one or more oxide structures to avoid parasitic diodes, the one or more oxide structures being provided on the p-type substrate.

8. Een versterkerschakeling volgens één van de conclu- sies 3-5 met het kenmerk, dat de diodes die de paren van anti- parallelle diodes vormen zijn aangebracht als lateraal geori- enteerde diodes bovenop een oxide structuur om parasitaire di- odes te vermijden, waarbij de I-V karakteristiek van de res- pectieve diodes is bepaald door de breedte van een ongesilicideerde zone tussen een p-type polysiliciumstructuur en een n-type polysiliciumstructuur.An amplifier circuit according to any one of claims 3 to 5, characterized in that the diodes forming the pairs of anti-parallel diodes are arranged as laterally oriented diodes on top of an oxide structure to avoid parasitic diodes, wherein the I-V characteristic of the respective diodes is determined by the width of an unsilicided zone between a p-type polysilicon structure and an n-type polysilicon structure.

9. Een akoestisch samenstel omvattende een omzetter en een versterkerschakeling volgens één van de conclusies 3-8, waarbij een uitgangsvoltage van de omzetter een ingangsvoltage naar de versterkerschakeling voorziet.An acoustic assembly comprising a converter and an amplifier circuit according to any one of claims 3-8, wherein an output voltage of the converter provides an input voltage to the amplifier circuit.

10. Een akoestisch samenstel volgens conclusie 9 met het kenmerk, dat de versterkerschakeling met van een ingangs- capaciteit (C in), en dat de omzetter een MEMS microfoon is met een MEMS capaciteit (C MEMS).An acoustic assembly according to claim 9, characterized in that the amplifier circuit has an input capacitance (C in), and the converter is a MEMS microphone with a MEMS capacitance (C MEMS).

11. Een akoestisch samenstel volgens conclusie 10 met het kenmerk, dat in het geval dat het tweede knooppunt van de eerste impedantieschakeling (D1, D2) werkend is verbonden met de uitgang van de versterker via een eerste wisselstroom koppelcondensator (C b), de capaciteit van de eerste 40 wisselstroom koppelcondensator (C b} kleiner of gelijk is aan een som van de MEMS capaciteit (C MEMS) en de ingangscapaci- teit (C in) van de versterkerschakeling.An acoustic assembly according to claim 10, characterized in that in case the second node of the first impedance circuit (D1, D2) is operably connected to the output of the amplifier via a first alternating current coupling capacitor (Cb), the capacitance of the first 40 AC coupling capacitor (Cb} is less than or equal to a sum of the MEMS capacitance (CMEMS) and the input capacitance (Cin) of the amplifier circuit.

12. Een akoestisch samenstel volgens conclusie 10 met het kenmerk, dat in het geval dat het tweede knooppunt van de eerste impedantieschakeling (D1, D2) werkend is verbonden met de uitgang van de versterker via de eerste wisselstroom koppelcondensator (C b), een tijdsconstante ingesteld door de eerste wisselstroom koppelcondenstator (C b) in combinatie met de tweede impedantieschakeling (D3, D4) kleiner is dan een tijdsconstante ingesteld door de som van de MEMS capaciteit (C MEMS} en de ingangscapaciteit (C in) van de versterkerscha- keling in combinatie met de eerste impedantieschakeling (D1, D2).An acoustic assembly according to claim 10, characterized in that in case the second node of the first impedance circuit (D1, D2) is operably connected to the output of the amplifier via the first alternating current coupling capacitor (Cb), a time constant set by the first alternating current coupling capacitor (C b) in combination with the second impedance circuit (D3, D4) is less than a time constant set by the sum of the MEMS capacitance (C MEMS} and the input capacitance (C in) of the amplifier circuit in combination with the first impedance circuit (D1, D2).

13. Een akoestisch samenstel volgens één van de con- clusies 10-12 met het kenmerk, dat het akoestisch samenstel verder een oplaadschakeling omvat voor het laden van de MEMS capaciteit van de MEMS microfoon, de oplaadschakeling omvat- tende a) een spanningsomzetter (V bias) met een uitgang, b) een eerste impedantieschakeling (D7, D8) met een eerste impedantie, de eerste impedantieschakeling (D7, D8) om- vattende een eerste en een tweede knooppunt, waarbij het eerste knooppunt werkend verbonden is aan de MEMS micro- foon, en c) een tweede impedantieschakeling (D9, D10) met een tweede impedantie, de tweede impedantieschakeling (DS, D10) om- vattende een eerste en een tweede knooppunt, waarbij het eerste knooppunt werkend verbonden is met het tweede knooppunt van de eerste impedantieschakeling (D7, D8), en waarbij het tweede knooppunt werkend verbonden is met de uitgang van de spanningsomzetter (V bias) waarbij de eerste en tweede impedantieschakelingen (D7, D8), (D9, D10) verbonden zijn in serie en waarbij de eerste en tweede impedantieschakelingen (D7, D8), (DS, D10) elk één of meer halfgeleiderelementen (D7, D8, D9, D10) omvatten, en waarbij de eerste en tweede impedantieschakelingen (D7, D8), (D9, D10) elk de karakteristiek van een paar anti-parallelle diodes verschaffen.An acoustic assembly according to any one of claims 10-12, characterized in that the acoustic assembly further comprises a charging circuit for charging the MEMS capacitance of the MEMS microphone, the charging circuit comprising a) a voltage converter (V bias) having an output, b) a first impedance circuit (D7, D8) having a first impedance, the first impedance circuit (D7, D8) comprising a first and a second node, the first node operably connected to the MEMS micro phone, and c) a second impedance circuit (D9, D10) having a second impedance, the second impedance circuit (DS, D10) comprising a first and a second node, the first node being operably connected to the second node of the first impedance circuit (D7, D8), and wherein the second node is operably connected to the output of the voltage converter (V bias) wherein the first and second impedance circuits (D7, D8), (D9, D10) are connected in series and wherein the first and second impedance circuits (D7, D8), (DS, D10) each comprise one or more semiconductor elements (D7, D8, D9, D10), and wherein the first and second impedance circuits (D7, D8), ( D9, D10) each provide the characteristic of a pair of anti-parallel diodes.

14. Een akoestisch samenstel volgens conclusie 13 met 40 het kenmerk, dat de eerste en tweede impedantieschakelingen14. An acoustic assembly according to claim 13, characterized in that the first and second impedance circuits

(D7, D8), (D9, D10}) elk een paar anti-parallelle diodes omvat gearrangeerd in een gestapelde opstelling bovenop een p-type substraat om parasitaire diodes te vermijden.(D7, D8), (D9, D10}) each comprises a pair of anti-parallel diodes arranged in a stacked arrangement on top of a p-type substrate to avoid parasitic diodes.

15. Een hoortoestel, zoals een hoorapparaat, in-oor luidsprekers, oordopjes en dergelijke met het kenmerk, dat het hoortoestel een akoestisch samenstel omvat volgens één van de conclusies 9 - 14.A hearing aid, such as a hearing aid, in-ear loudspeakers, earplugs and the like, characterized in that the hearing aid comprises an acoustic assembly according to any one of claims 9-14.