NL2016141A - A new low cost frequency dividing circuit and its control method. - Google Patents

A new low cost frequency dividing circuit and its control method. Download PDF

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Publication number
NL2016141A
NL2016141A NL2016141A NL2016141A NL2016141A NL 2016141 A NL2016141 A NL 2016141A NL 2016141 A NL2016141 A NL 2016141A NL 2016141 A NL2016141 A NL 2016141A NL 2016141 A NL2016141 A NL 2016141A
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output
input
module
counter
coupled
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NL2016141A
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Dutch (nl)
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NL2016141B1 (en
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Kang Cheng
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Univ Fu Zhou
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/48—Gating or clocking signals applied to all stages, i.e. synchronous counters with a base or radix other than a power of two

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  • Logic Circuits (AREA)

Abstract

A frequency dividing circuit and its control method is described. In this circuit, the frequency dividing input circuit is connected with a first counting circuit and a counting and setting circuit. The first counting circuit is connected with a second counting circuit, a first comparing circuit, a first threshold input circuit and the counting and setting circuit. The second counting circuit is connected with the counting and setting circuit, a second threshold input circuit and a second comparing circuit. The first comparing circuit is connected with the first threshold input circuit and the second comparing circuit. The second threshold input circuit is connected with the second comparing circuit. The second comparing circuit is connected with the counting and setting circuit. This method achieves frequency division by setting two thresholds and combining the output and input characteristics of comparator and counter by changing the dial switch without any circuit modification.

Description

A new low cost frequency dividing circuit and its control method
Technical Field
The invention relates to a new low cost frequency dividing circuit and its control method.
Technical Background of the invention
The traditional frequency dividing circuit is shown in Figure 1, which is realized by series T trigger, the disadvantages are: If we want to change the frequency speed in use, we not only have to change the hardware connection of the circuit, but also need to increase the number of necessary components, which increase the unnecessary costs and which is more cumbersome. In addition, the frequency of the frequency dividing circuit is only 2 times, such as 2,8,16, and it can not divide the frequency in arbitrary multiples, which greatly affecte the convenience of the circuit. Due to the widespread application of the frequency dividing circuit, it is urgent to put forward a kind of frequency dividing circuit which is not limited to the basic multiples of 2, and which is simple and efficient and spands low cost.
Summary of the utility model
The invention aims to provide a new low cost frequency dividing circuit and its control method in order to overcome the defects existing in the prior art and achieve the setting of arbitrary frequency dividing ratio.
To achieve the above purpose, the technology options of this invention are: a new low cost frequency dividing circuit, including a frequency dividing input module, the first end of the frequency dividing input module is connected to the first end of a first counting module, the second end of the first counting module is connected to the first end of a first threshold input module, the third end of the first counting module is connected to the fisrt end of a first comparing module, the fourth end of the first counting module is connected to the first end of a second counting module, the second end of the first threshold input module is connected to the second end of the first comparing module, the second end of the second counting module is connected to the first end of a second threshold input module, the third end of the second counting module is connected to the first end of a second comparing module, the second end of the second threshold input module is connected to the second end of the second comparing module, the third end of the second comparing module is connected to the third end of the first comparing module, the fourth end of the second comparing module is used as the output end of the new low cost frequency dividing circuit and is connected to the first end of a counting and setting module, the second end of the counting and setting module is connected to the second end of the frequency dividing input module, the third end of the counting and setting module is connected to the fifth end of the first counting module and the fourth end of the second counting module.
Further, the frequency dividing input module includes a first NAND circuit and a second NAND circuit, the first input end of the first NAND circuit is used to input reduced pulse signal, the first input end of the second NAND circuit is used to input plus pulse signal, the second input end of the first NAND circuit is connected to the second input end of the second NAND circuit, which is used as the second end of the frequency dividing input module, the output end of the first NAND circuit and the output end of the second NAND circuit is both connected to the first counting module.
Further, the first counting module includes a first counter 40193, the CP+ end of the first counter 40193 is connected with the output end of the second NAND circuit, the CP- end of the first counter 40193 is connected with the output end of the first NAND circuit, the R end of the first counter 40193 is used as the fifth end of the first counting module.
Further, the first comparing module includes a first comparator 4585; the AO end , A1 end, A2 end and A3 end of the first comparator 4585 are respectively connected to the Q1 end, Q2 end, Q3 end, Q4 end of the first counter 40193; the (A>B)IN end and the (A=B)IN end of the first comparator 4585 is connected with high level, the (A<B)IN end of the first comparator 4585 is earthed.
Further, the first threshold input module includes a first dial switch SI, the first input end to the fourth input end of the first dial switch SI are both connected with high level, the first output end to the fourth output end of the first dial switch SI are respectively connected to the DPI end, DP2 end, DP3 end, DP4 end of the first counter 40193, the first output end of the first dial switch SI is also connected with the first end of a fourth resistance(R4) and the B3 end of the first comparator 4585, the second output end of the first dial switch S1 is also connected with the first end of a third resistance(R3) and the B2 end of the first comparator 4585, the third output end of the first dial switch SI is also connected with the first end of a second resistance(R2) and the B1 end of the first comparator 4585, the fourth output end of the first dial switch SI is also connected with the first end of a first resistance(Rl) and the BO end of the first comparator 4585; the second end of the first resistance(Rl), the second end of the second resistance(R2), the second end of the third resistance(R3) and the second end of the fourth resistance(R4) are both earthed.
Further, the second counting module includes a second counter 40193, the CP+ end of the second counter 40193 is connected to the CO end of the first counter 40193, the CP- end of the second counter 40193 is connected to the BO end of the first counter 40193, the R end of the second counter 40193 is used as the fourth end of the second counting module, the CO end of the second counter 40193 is connected to the PE end of the first counter 40193 and the PE end of the second counter 40193 .
Further, the second comparing module includes a second comparator 4585; the A0 end , A1 end, A2 end and A3 end of the second comparator 4585 are respectively connected to the Q1 end, Q2 end, Q3 end, Q4 end of the second counter 40193; the (A>B)IN end of the second comparator 4585 is connected with high level, the (A=B)IN end of the second comparator 4585 is connected to the (A=B)OUT end of the first comparator 4585, the (A<B)IN end of the second comparator 4585 is connected to (A<B)OUT end of the first comparator 4585, the (A>B)OUT end of the second comparator 4585 is used as fourth end of the second comparing module.
Further, the second threshold input module includes a second dial switch S2, the first input end to the fourth input end of the second dial switch S2 are both connected with high level, the first output end to the fourth output end of the second dial switch S2 are respectively connected to the DPI end, DP2 end, DP3 end, DP4 end of the second counter 40193, the first output end of the second dial switch S2 is also connected with the first end of a eighth resistance(R8) and the B3 end of the second comparator 4585, the second output end of the second dial switch S2 is also connected with the first end of a seventh resistance(R7) and the B2 end of the second comparator 4585, the third output end of the second dial switch S2 is also connected with the first end of a sixth resistance(Ró) and the B1 end of the second comparator 4585, the fourth output end of the second dial switch S2 is also connected with the first end of a fifth resistance(R5) and the BO end of the second comparator 4585; the second end of the fifth resistance(R5), the second end of the sixth resistance(Ró), the second end of the seventh resistance(R7) and the second end of the eighth resistance(R8) are both earthed.
Further, the counting and setting module includes a third NAND circuit and a NOR circuit, the first input end of the third NAND circuit is used as the second end of the counting and setting module, the second input end of the third NAND circuit is used as the first end of the counting and setting modul, the output end of the third NAND circuit is connected to the input end of the NOR circuit, the output end of the NOR circuit is used as the third end of the counting and setting module.
Further, a control method of a new low cost frequency dividing circuit according to the content mentioned above is : set the first threshold N by the first dial switch S1 in the first threshold input module, set the second threshold M by the second dial switch S2 in the second threshold input module, when the setting is completed, provide power to all the modules of the frequency dividing circuit, the frequency dividing input module input the signal to be divided to the CP+ end of the first counter 40193 in first counting module, the first counter 40193 counts the signal to be divided, the first comparator 4585 in first comparing module recieves the first counting output from the output end of the first counter 40193, then compare the first counting output with the the first threshold N, the CO end of the first counter 40193 gives a pulse when the first counting output is equal to the first threshold N; the first counter 40193 transmits the pulse to the CP+ end of the second counter 40193, the second counter 40193 counts the pulse; the second comparator 4585 in second comparing module recieves the second counting output from the output end of the second counter 40193, then compare the second counting output with the the second threshold M, the (A>B) OUT end of the second comparator 4585 gives frequency pulse signal when the second counting output is equal to the second threshold M, in order to achieve the M*16+N frequency division of the signal to be divided; transmit the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restart counting, where N or M is a positive integer greater than or equal to 1.
Compared with the prior art, the invention has the following advantages: The invention relates to a new low cost frequency dividing circuit and its control method, which can divide the frequency in any integer multiple, and which is not limited to the existing frequency dividing circuit that can only divide the frequency in 2 times. The invention can achieve frequency division by setting two thresholds and combining the output and input characteristics of comparator and counter. The invention can set frequency division multiple with any integer simply and efficiently only by changing the dial switch without any hardware circuit modification. The invention greatly reduce the cost not using any programmable logic devices or micro control processor.
Brief description of the drawings
Figure 1 shows the circuit diagram of the frequency division circuit used in the conventional technology.
Figure 2 shows the circuit principle diagrama of the new low cost frequency dividing circuit in this invention.
Figure 3 shows the schematic diagram of circuit connection of the new low cost frequency dividing circuit in this invention.
Detailed Description of the invention
To allow the above features and advantages of this invention become more fully understood, especially cite the example below, and with the accompanying drawings, described in detail below, but the invention is not limited to this.
Example 1: As shown in figure 2, a new low cost frequency dividing circuit, including a frequency dividing input module, the first end of the frequency dividing input module is connected to the first end of a first counting module, the second end of the first counting module is connected to the first end of a first threshold input module, the third end of the first counting module is connected to the fisrt end of a first comparing module, the fourth end of the first counting module is connected to the first end of a second counting module, the second end of the first threshold input module is connected to the second end of the first comparing module, the second end of the second counting module is connected to the first end of a second threshold input module, the third end of the second counting module is connected to the first end of a second comparing module, the second end of the second threshold input module is connected to the second end of the second comparing module, the third end of the second comparing module is connected to the third end of the first comparing module, the fourth end of the second comparing module is used as the output end of the new low cost frequency dividing circuit and is connected to the first end of a counting and setting module, the second end of the counting and setting module is connected to the second end of the frequency dividing input module, the third end of the counting and setting module is connected to the fifth end of the first counting module and the fourth end of the second counting module.
In this example, the frequency dividing input module includes a first NAND circuit U1 and a second NAND circuit U2 , the first input end of the first NAND circuit U1 is used to input reduced pulse signal, the first input end of the second NAND circuit U2 is used to input plus pulse signal, the second input end of the first NAND circuit U1 is connected to the second input end of the second NAND circuit U2, which is used as the second end of the frequency dividing input module, the output end of the first NAND circuit UI and the output end of the second NAND circuit U2 is both connected to the first counting module.
In this example, as shown in figure 3 ,the first counting module includes a first counter 40193, the CP+ end(pin 5) of the first counter 40193 is connected with the output end of the second NAND circuit U2, the CP- end(pin 4) of the first counter 40193 is connected with the output end of the first NAND circuit Ul, the R end(pin 14) of the first counter 40193 is used as the fifth end of the first counting module, which is connected to the output end of the NOR circuit in counting and setting module.
In this example, the first comparing module includes a first comparator 4585; the AO end(pin 10), A1 end(pin 7), A2 end(pin 2) and A3 end(pin 15) of the first comparator 4585 are respectively connected to the Q1 end(pin 3), Q2 end(pin 2), Q3 end(pin 6), Q4(pin 7) end of the first counter 40193; the (A>B)IN end(pin 4) and the (A=B)IN end(pin 6) of the first comparator 4585 is connected with high level, the (A<B)IN end(pin 5) of the first comparator 4585 is earthed.
In this example, the first threshold input module includes a first dial switch Sl( which is a 4 digit dialing switch), the first input end to the fourth input end of the first dial switch S1 are both connected with high level, the first output end to the fourth output end of the first dial switch SI are respectively connected to the DPI end(pin 15), DP2 end(pin 1), DP3 end(pin 10), DP4 end(pin 9) of the first counter 40193, the first output end of the first dial switch SI is also connected with the first end of a fourth resistance(R4) and the B3 end(pin 14) of the first comparator 4585, the second output end of the first dial switch SI is also connected with the first end of a third resistance(R3) and the B2 end(pin 1) of the first comparator 4585, the third output end of the first dial switch SI is also connected with the first end of a second resistance(R2) and the B1 end(pin 9) of the first comparator 4585, the fourth output end of the first dial switch SI is also connected with the first end of a first resistance(Rl) and the B0 end(pin 11) of the first comparator 4585; the second end of the first resistance(Rl), the second end of the second resistance(R2), the second end of the third resistance(R3) and the second end of the fourth resistance(R4) are both earthed.
In this example, as shown in figure 3,the second counting module includes a second counter 40193, the CP+ end(pin 12) of the second counter 40193 is connected to the CO end(pin 12) of the first counter 40193, the CP- end(pin 4) of the second counter 40193 is connected to the BO end(pin 13) of the first counter 40193, the R end(pin 14) of the second counter 40193 is used as the fourth end of the second counting module, the CO end(pin 12) of the second counter 40193 is connected to the PE end(pin 11) of the first counter 40193 and the PE end(pin 11) of the second counter 40193 .
In this example, the second comparing module includes a second comparator 4585; the A0 end(pin 10) , A1 end(pin 7), A2 end(pin 2) and A3 end(pin 1) of the second comparator 4585 are respectively connected to the Q1 end(pin 3), Q2 end(pin 2), Q3 end(pin 6), Q4 end(pin 7) of the second counter 40193; the (A>B)IN end(pin 4) of the second comparator 4585 is connected with high level(5V), the (A=B)IN end(pin 6) of the second comparator 4585 is connected to the (A=B)OUT end(pin 3) of the first comparator 4585, the (A<B)IN end(pin 6) of the second comparator 4585 is connected to (A<B)OUT end(pin 12) of the first comparator 4585, the (A>B)OUT end(pin 13) of the second comparator 4585 is used as fourth end of the second comparing module.
In this example, as shown in figure 3,the second threshold input module includes a second dial switch S2(which is a 4 digit dialing switch), the first input end to the fourth input end of the second dial switch S2 are both connected with high level, the first output end to the fourth output end of the second dial switch S2 are respectively connected to the DPI end(pin 15), DP2 end(pin 1), DP3 end(pin 10), DP4 end(pin 9) of the second counter 40193, the first output end of the second dial switch S2 is also connected with the first end of a eighth resistance(R8) and the B3 end(pin 14) of the second comparator 4585, the second output end of the second dial switch S2 is also connected with the first end of a seventh resistance(R7) and the B2 end(pin 1) of the second comparator 4585, the third output end of the second dial switch S2 is also connected with the first end of a sixth resistance(Ró) and the B1 end(pin 9) of the second comparator 4585, the fourth output end of the second dial switch S2 is also connected with the first end of a fifth resistance(R5) and the B0 end(pin 11) of the second comparator 4585; the second end of the fifth resistance(R5), the second end of the sixth resistance(R6), the second end of the seventh resistance(R7) and the second end of the eighth resistance(R8) are both earthed.
In this example, as shown in figure 3,the counting and setting module includes a third NAND circuit U4 and a NOR circuit U3, the first input end of the third NAND circuit U4 is used as the second end of the counting and setting module(which is connected to the second input end of the first NAND circuit U1 and the second input end of the second NAND circuit U2), the second input end of the third NAND circuit is used as the first end of the counting and setting modul(which is connected to the (A>B)OUT end of the second comparator 4585), the output end of the third NAND circuit U4 is connected to the input end of the NOR circuit U3, the output end of the NOR circuit U4 is used as the third end of the counting and setting module(which is connected to the R end of the first counter 40193 and the R end of the second counter 40193).
In order to let the technical personnel in the field to fully understand the invention of a new low cost frequency dividing circuit, following are the control method combined with the specific instructions. A control method of a new low cost frequency dividing circuit according to the content mentioned above is : set the first threshold N by the first dial switch SI in the first threshold input module, set the second threshold M by the second dial switch S2 in the second threshold input module, when the setting is completed, provide power to all the modules of the frequency dividing circuit, the frequency dividing input module input the signal to be divided to the CP+ end of the first counter 40193 in first counting module, the first counter 40193 counts the signal to be divided, the first comparator 4585 in first comparing module recieves the first counting output from the output end of the first counter 40193(the Q1 end to Q4 end of the first counter 40193), then compare the first counting output with the the first threshold N, the CO end of the first counter 40193 gives a pulse when the first counting output is equal to the first threshold N; the first counter 40193 transmits the pulse to the CP+ end of the second counter 40193, the second counter 40193 counts the pulse; the second comparator 4585 in second comparing module recieves the second counting output from the output end of the second counter 40193(the Q1 end to Q4 end of the second counter 40193), then compare the second counting output with the the second threshold M, the (A>B) OUT end of the second comparator 4585 gives frequency pulse signal when the second counting output is equal to the second threshold M, in order to achieve the M*16+N frequency division of the signal to be divided; transmit the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restart counting, where N or M is a positive integer greater than or equal to 1.
In this example, the first comparator 4585 and the second comparator 4585 are both 4 bit binary comparator. Input P to pin 10, pin 7, pin 2, pin 2 and pin 15, input Q to pin 11, pin 9, pin 1, pin 14, compare P with Q, if P>Q, pin 13 output high level; if P=Q, pin 3 output high level; if P<Q, pin 12 output high level.
In this example, the first counter 40193 and the second counter 40193 are both 4 bit binary reversible counter. The counter plus 1 when pin 5 is at the rising edge, the counter minus 1 when pin 4 is at the rising edge. The counter can not work while the pin 4 and the pin 5 are both at the rising edge at the same time. The first counter 40193 and the second counter 40193 can both output counting value through pin 3, pin 2, pin 6 and pin 7.
The invention described above is only a preferred embodiment, where the invention patent under this range equalization changes and modifications made, also belong to the scope of the invention.
In short the invention can be described as follows:

Claims (10)

1. Een goedkope frequentiedelingschakeling, met het kenmerk dat deze een frequentiedelinginvoermodule bevat, waarbij een eerste uitgang van de frequentiedeelinvoermodule gekoppeld is met een eerste ingang van een eerste telmodule, een tweede ingang van de eerste telmodule gekoppeld is met een eerste uitgang van een eerste drempelwaardeinvoermodule, een derde uitgang van de eerste telmodule gekoppeld is met een eerste ingang van een eerste vergelijkingsmodule, een vierde uitgang van de eerste telmodule gekoppeld is met een eerste ingang van een tweede telmodule, een tweede uitgang van de eerste drempelwaardeinvoermodule gekoppeld is met een tweede ingang van de eerste vergelijkingsmodule, een tweede ingang van de tweede telmodule gekoppeld is met een eerste uitgang van een tweede drempelwaardeinvoermodule, een derde ingang van de tweede telmodule gekoppeld is met een eerste uitgang van een tweede vergelijkingsmodule , een tweede ingang van de tweede drempelwaardeinvoermodule gekoppeld is met een tweede uitgang van de tweede vergelijkingsmodule, een derde ingang van de tweede vergelijkingsmodule gekoppeld is met een derde uitgang van de eerste vergelijkingsmodule, waarbij een vierde uitgang van de tweede vergelijkingsmodule wordt gebruikt als de uitvoer van de goedkope frequentiedelingschakeling en gekoppeld is met een eerste ingang van een tel- en instelmodule, waarbij een tweede uitgang van de tel- en instelmodule gekoppeld is met een tweede ingang van de frequentiedelinginvoermodule, een derde uitgang van de tel- en instelmodule gekoppeld is met een vijfde ingang van de eerste telmodule en een vierde ingang van de tweede telmodule.An inexpensive frequency division circuit, characterized in that it comprises a frequency division input module, a first output of the frequency division input module being coupled to a first input of a first counting module, a second input of the first counting module being coupled to a first output of a first threshold value input module , a third output of the first counting module is coupled to a first input of a first comparison module, a fourth output of the first counting module is coupled to a first input of a second counting module, a second output of the first threshold value input module is coupled to a second input of the first comparison module, a second input of the second counting module is coupled to a first output of a second threshold value input module, a third input of the second counting module is coupled to a first output of a second comparison module, a second input of the second threshold value input module is coupled i s with a second output of the second comparison module, a third input of the second comparison module is coupled to a third output of the first comparison module, wherein a fourth output of the second comparison module is used as the output of the low-cost frequency division circuit and is coupled to a first input of a counting and setting module, wherein a second output of the counting and setting module is coupled to a second input of the frequency division input module, a third output of the counting and setting module is coupled to a fifth input of the first counting module and a fourth input of the second counting module. 2. Een goedkope frequentiedelingschakeling volgens conclusie 1, met het kenmerk, dat de frequentiedelinginvoermodule een eerste en een tweede NAND schakeling bevat, waarbij een eerste ingang van de eerste NAND schakeling gebruikt wordt voor het invoeren van een afname pulse signaal, een eerste ingang van de tweede NAND schakeling gebruikt wordt voor het invoeren van een plus pulse signaal, waarbij een tweede ingang van de eerste NAND schakeling gekoppeld is met een tweede ingang van de tweede NAND schakeling, die gebruikt wordt als tweede ingang van de frequentiedelinginvoermodule, waarbij de uitvoer van de eerste NAND schakeling en de uitvoer van de tweede NAND schakeling beid gekoppeld zijn met de eerste telmodule.An inexpensive frequency division circuit according to claim 1, characterized in that the frequency division input module comprises a first and a second NAND circuit, wherein a first input of the first NAND circuit is used to input a decrease pulse signal, a first input of the second NAND circuit is used to input a plus pulse signal, a second input of the first NAND circuit being coupled to a second input of the second NAND circuit, which is used as the second input of the frequency division input module, the output of the first NAND circuit and the output of the second NAND circuit are both coupled to the first counting module. 3. Een goedkope frequentiedelingschakeling volgens conclusie 2, met het kenmerk, dat de eerste telmodule een eerste teller 40193 bevat, waarbij het CP+ eind van de eerste teller 40193 gekoppeld is met de uitvoer van de tweede NAND schakeling, het CP-eind van de eerste teller 40193 gekoppeld is met de uitvoer van de eerste NAND schakeling, waarbij het R eind van de eerste teller 401934 gebruikt wordt als de vijfde ingang van de eerste telmodule.An inexpensive frequency division circuit according to claim 2, characterized in that the first counting module comprises a first counter 40193, the CP + end of the first counter 40193 being coupled to the output of the second NAND circuit, the CP end of the first counter 40193 is coupled to the output of the first NAND circuit, the R end of the first counter 401934 being used as the fifth input of the first counting module. 4. Een goedkope frequentiedelingschakeling volgens conclusie 3, met het kenmerk, dat de eerste vergelijkingsmodule een eerste vergelijker 4585 bevat, waarbij het A0 eind, het Al eind het A2 eind en het A3 eind van de eerste vergelijker 4585 gekoppeld zijn met respectievelijk het Ql, Q2, Q3 en Q4 eind van de eerste teller 40193, en waarbij het (A>B)IN eind en het (A=B)IN eind van de eerste vergelijker 4585 gekoppeld is met een hoog niveau en het (A<B)in eind van de eerste vergelijker 4585 geaard is.An inexpensive frequency division circuit according to claim 3, characterized in that the first comparison module comprises a first comparator 4585, wherein the A0 end, the A1 end, the A2 end and the A3 end of the first comparator 4585 are coupled to the Q1, respectively Q2, Q3 and Q4 end of the first counter 40193, and wherein the (A> B) IN end and the (A = B) IN end of the first comparator 4585 is coupled to a high level and the (A <B) in 4585 is grounded at the end of the first comparator 4585. 5. Een goedkope frequentiedelingschakeling volgens conclusie 4, met het kenmerk, dat de eerste drempelwaardeinvoermodule een eerste dial schakelaar SI bevat, waarbij de eerste tot en met de vierde ingang van de eerste dial schakelaar SI gekoppeld zijn met een hoog niveau, de eerste tot en met vierde uitgang van de eerste dial schakelaar S1 gekoppeld zijn met respectievelijk het DPI, DP2, DP3 en DP4 eind van de eerste teller 40193, waarbij de eerste uitgang van de eerste dial schakelaar SI ook gekoppeld is met een eerst eind van een vierde weerstand (R4) en het B3 einde van de eerste vergelijker 4585, de tweede uitgang van de eerste dial schakelaar SI ook gekoppeld is met een eerst eind van een derde weerstand (R3) en het B2 einde van de eerste vergelijker 4585, de derde uitgang van de eerste dial schakelaar SI ook gekoppeld is met een eerst eind van een tweede weerstand (R2) en het BI einde van de eerste vergelijker 4585, de vierde uitgang van de eerste dial schakelaar SI ook gekoppeld is met een eerst eind van een eerste weerstand (Rl) en het B0 einde van de eerste vergelijker 4585, waarbij het tweede eind van de eerste weerstand (Rl), het tweede eind van de tweede weerstand (R2), het tweede eind van de derde weerstand (R3) en het tweede eind van de vierde weerstand (R4) alle geaard zijn.An inexpensive frequency division circuit according to claim 4, characterized in that the first threshold value input module comprises a first dial switch S1, the first to fourth inputs of the first dial switch S1 being coupled to a high level, the first to with fourth output of the first dial switch S1 being coupled to the DPI, DP2, DP3 and DP4 end of the first counter 40193, respectively, the first output of the first dial switch S1 also being coupled to a first end of a fourth resistor ( R4) and the B3 end of the first comparator 4585, the second output of the first dial switch S1 is also coupled to a first end of a third resistor (R3) and the B2 end of the first comparator 4585, the third output of the first dial switch S1 is also coupled to a first end of a second resistor (R2) and the BI end of the first comparator 4585, the fourth output of the first dial switch S1 is also coupled is with a first end of a first resistor (R1) and the B0 end of the first comparator 4585, the second end of the first resistor (R1), the second end of the second resistor (R2), the second end of the third resistor (R3) and the second end of the fourth resistor (R4) are all grounded. 6. Een goedkope frequentiedelingschakeling volgens conclusie 5, met het kenmerk, dat de tweede telmodule een tweede teller 40193 bevat, waarbij het CP+ eind van de tweed teller 40193 gekoppeld is met het CO eind van de eerste teller 40193, het CP-eind van de tweede teller gekoppeld is met het BO eind van de eerste teller 40193, het R eind van de tweede teller gebruikt wordt als de vierde input van de tweede telmodule, het CO eind van de tweede teller 40193 gekoppeld is met het PE eind van de eerste teller 40193 en het PE eind van de tweede teller 40193.An inexpensive frequency division circuit according to claim 5, characterized in that the second counting module comprises a second counter 40193, wherein the CP + end of the second counter 40193 is coupled to the CO end of the first counter 40193, the CP end of the second counter is coupled to the BO end of the first counter 40193, the R end of the second counter is used as the fourth input of the second counter module, the CO end of the second counter 40193 is coupled to the PE end of the first counter 40193 and the PE end of the second counter 40193. 7. Een goedkope frequentiedelingschakeling volgens conclusie 6, met het kenmerk, dat de tweede vergelijkingsmodule een tweede vergelijker 4585 bevat, waarbij het A0 eind, het Al eind het A2 eind en het A3 eind van de tweede vergelijker 4585 gekoppeld zijn met respectievelijk het Ql, Q2, Q3 en Q4 eind van de tweede teller 40193, en waarbij het (A>B)IN eind van de tweede vergelijker 4585 gekoppeld is met een hoog niveau, het (A=B)IN eind van de tweede vergelijker 4585 gekoppeld is met het (A=B)OUT eind van de eerste vergelijker 4585, het (A<B)IN eind van de tweede vergelijker 4585 gekoppeld is met het (A<B)OUT eind van de eerste vergelijker 4585, waarbij het (A>B)OUT eind van de tweede vergelijker 4585 gebruikt wordt als de vierde uitgang van de tweede vergelijkingsmodule.An inexpensive frequency division circuit according to claim 6, characterized in that the second comparison module comprises a second comparator 4585, wherein the A0 end, the A1 end, the A2 end and the A3 end of the second comparator 4585 are coupled to the Q1, respectively Q2, Q3 and Q4 end of the second counter 40193, and where the (A> B) IN end of the second comparator 4585 is coupled to a high level, the (A = B) IN end of the second comparator 4585 is coupled to the (A = B) OUT end of the first comparator 4585, the (A <B) IN end of the second comparator 4585 is coupled to the (A <B) OUT end of the first comparator 4585, the (A> B) The OUT end of the second comparator 4585 is used as the fourth output of the second comparison module. 8. Een goedkope frequentiedelingschakeling volgens conclusie 7, met het kenmerk, dat de tweede drempelwaardeinvoermodule een tweede dial schakelaar S2 bevat, waarbij de eerste tot en met de vierde ingang van de tweede dial schakelaar S2 gekoppeld zijn met een hoog niveau, de eerste tot en met vierde uitgang van de tweede dial schakelaar S2 gekoppeld zijn met respectievelijk het DPI, DP2, DP3 en DP4 eind van de tweede teller 40193, waarbij de eerste uitgang van de tweede dial schakelaar S2 ook gekoppeld is met een eerst eind van een achtste weerstand (R8) en het B3 einde van de tweede verge lijker 4585, de tweede uitgang van de tweede dial schakelaar S2 ook gekoppeld is met een eerst eind van een zevende weerstand (R7) en het B2 einde van de tweede vergelijker 4585, de derde uitgang van de tweede dial schakelaar S2 ook gekoppeld is met een eerst eind van een zesde weerstand (R6) en het B1 einde van de tweede vergelijker 4585, de vierde uitgang van de tweede dial schakelaar S2 ook gekoppeld is met een eerst eind van een vijfde weerstand (R5) en het B0 einde van de tweede vergelijker 4585, waarbij het tweede eind van de vijfde weerstand (R5), het tweede eind van de zesde weerstand (R6), het tweede eind van de zevende weerstand (R7) en het tweede eind van de achtste weerstand (R8) alle geaard zijn.An inexpensive frequency division circuit according to claim 7, characterized in that the second threshold value input module comprises a second dial switch S2, the first to fourth inputs of the second dial switch S2 being coupled to a high level, the first to and with the fourth output of the second dial switch S2 coupled to the DP1, DP2, DP3 and DP4 end of the second counter 40193, respectively, the first output of the second dial switch S2 also being coupled to a first end of an eighth resistor ( R8) and the B3 end of the second comparator 4585, the second output of the second dial switch S2 is also coupled to a first end of a seventh resistor (R7) and the B2 end of the second comparator 4585, the third output of the second dial switch S2 is also coupled to a first end of a sixth resistor (R6) and the B1 end of the second comparator 4585, the fourth output of the second dial switch S2 is also coupled is with a first end of a fifth resistor (R5) and the B0 end of the second comparator 4585, the second end of the fifth resistor (R5), the second end of the sixth resistor (R6), the second end of the seventh resistor (R7) and the second end of the eighth resistor (R8) are all grounded. 9. Een goedkope frequentiedelingschakeling volgens conclusie 8, met het kenmerk, dat de tel- en instelmodule een derde NAND schakeling en een NOR schakeling bevat, waarbij een eerste ingang van de derde NAND schakeling gebruikt wordt als de tweede uitgang van de tel- en instelmodule, waarbij een tweede ingang van de derde NAND schakeling gebruikt wordt als de eerste ingang van de tel- in instelmodule, waarbij de uitvoer van de NOR schakeling gebruikt wordt als een derde uitgang van de tel- en instelmodule.An inexpensive frequency division circuit according to claim 8, characterized in that the counting and setting module comprises a third NAND circuit and a NOR circuit, wherein a first input of the third NAND circuit is used as the second output of the counting and setting module wherein a second input of the third NAND circuit is used as the first input of the count-in setting module, the output of the NOR circuit being used as a third output of the counting and setting module. 10. Een werkwijze voor het bedienen van een geodkope frequentiedelingschakeling volgens conclusie 9, met het kenmerk, dat een eerste drempelwaarde N wordt ingesteld in de eerste drempelwaardeinvoermodule door de eerste dial schakeling S1, een tweede drempelwaarde M wordt ingesteld in de tweede drempelwaardeinvoermodule door de eerste dial schakeling S2, en - wanneer de drempelwaarden zijn ingesteld alle modules van de frequentiedelingschakeling worden bekrachtigd, de frequentiedeelinvoermodule het te delen signaal toevoert aan het CP+ eind van de eerste teller 40193 in de eerste telmodule, - de eerste teller 40193 het te delen signaal telt, - de eerste vergelijker 4585 in de eerste vergelijkingsmodule de eerste count output ontvangt van de uitvoer van de eerste teller 40193, vervolgens de eerste count output vergelijkt met de eerste drempelwaarde N, waarbij het CO eind van de eerste teller 40193 een puls geeft wanneer de eerste count output gelijk is aan de eerste drempelwaarde N, de eerste teller 40193 de puls doorgeeft aan aan het CP+ eind van de tweede teller 40193 en de tweede teller 40193 de puls telt, - de tweede vergelijker 4585 en de tweede vergelijkinsgmodule een tweede count output ontvangt van de uitvoer van de tweede teller 40193 en - vervolgens de tweede count output vergelijkt met de tweede drempelwaarde M, waarbij het (A>B)OUT eind van de tweede vergelijker een frequentie puls signaal geeft wanneer de tweede count output gelijk is aan de tweede drempelwaarde M, teneinde een M* 16 +N deling van het te delen signaal te verkrijgen, doorgeven van het frequentie puls signaal aan het R eind van de eerste teller 40193 en het R eind van de tweede teller 40193 door de tel- en instelmodule voor het resetten en herstarten van het tellen, waarbij N and M een geheel positief getal zijn groter of gelijk aan 1.A method for operating an geo-low frequency division circuit according to claim 9, characterized in that a first threshold value N is set in the first threshold value input module by the first dial circuit S1, a second threshold value M is set in the second threshold value input module by the first dial circuit S2, and - when the threshold values are set, all modules of the frequency division circuit are energized, the frequency division input module applies the signal to be shared to the CP + end of the first counter 40193 in the first counting module, - the first counter 40193 counts the signal to be shared the first comparator 4585 in the first comparison module receives the first count output from the output of the first counter 40193, then compares the first count output with the first threshold value N, the CO end of the first counter 40193 giving a pulse when the first count output is equal to the first threshold value N, the e first counter 40193 transmits the pulse to the CP + end of the second counter 40193 and the second counter 40193 counts the pulse, - the second comparator 4585 and the second comparison module receives a second count output from the output of the second counter 40193 and - then compares the second count output with the second threshold value M, the (A> B) OUT end of the second comparator giving a frequency pulse signal when the second count output is equal to the second threshold value M, in order to divide M * 16 + N of the signal to be shared, passing the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restarting the counting, where N and M an integer positive number greater than or equal to 1.
NL2016141A 2015-04-25 2016-01-22 A new low cost frequency dividing circuit and its control method. NL2016141B1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2451271A1 (en) * 1974-10-29 1976-05-06 Licentia Gmbh Pulse value convertor for electricity meters - pulses corresponding to mains voltage and load current converted through matching elements
GB2235556A (en) * 1989-06-29 1991-03-06 Birt Electronic Systems Ltd Binary counting circuit
EP0480681A1 (en) * 1990-10-09 1992-04-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69624952T2 (en) * 1996-01-09 2003-08-28 Sanyo Electric Co Adjustable frequency divider
CN102102997A (en) * 2010-12-28 2011-06-22 威海华东电源有限公司 Random frequency division device for orthogonal serial output rotary encoder and implementation method thereof
CN204559543U (en) * 2015-04-25 2015-08-12 福州大学 A kind of novel low-cost frequency dividing circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2451271A1 (en) * 1974-10-29 1976-05-06 Licentia Gmbh Pulse value convertor for electricity meters - pulses corresponding to mains voltage and load current converted through matching elements
GB2235556A (en) * 1989-06-29 1991-03-06 Birt Electronic Systems Ltd Binary counting circuit
EP0480681A1 (en) * 1990-10-09 1992-04-15 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit

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