NL153721B - Werkwijze voor het vormen van elektrische verbindingen tussen een drager en een, in een uitsparing van de drager opgenomen halfgeleiderplaatje en voortbrengsel verkregen volgens deze werkwijze. - Google Patents
Werkwijze voor het vormen van elektrische verbindingen tussen een drager en een, in een uitsparing van de drager opgenomen halfgeleiderplaatje en voortbrengsel verkregen volgens deze werkwijze.Info
- Publication number
- NL153721B NL153721B NL666608622A NL6608622A NL153721B NL 153721 B NL153721 B NL 153721B NL 666608622 A NL666608622 A NL 666608622A NL 6608622 A NL6608622 A NL 6608622A NL 153721 B NL153721 B NL 153721B
- Authority
- NL
- Netherlands
- Prior art keywords
- carrier
- procedure
- obtained according
- electrical connections
- forming electrical
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/732—Location after the connecting process
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- H01L2224/73267—Layer and HDI connectors
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- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/05—Etch and refill
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/4981—Utilizing transitory attached element or associated separate material
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US466182A US3325882A (en) | 1965-06-23 | 1965-06-23 | Method for forming electrical connections to a solid state device including electrical packaging arrangement therefor |
Publications (2)
Publication Number | Publication Date |
---|---|
NL6608622A NL6608622A (xx) | 1966-12-27 |
NL153721B true NL153721B (nl) | 1977-06-15 |
Family
ID=23850828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
NL666608622A NL153721B (nl) | 1965-06-23 | 1966-06-22 | Werkwijze voor het vormen van elektrische verbindingen tussen een drager en een, in een uitsparing van de drager opgenomen halfgeleiderplaatje en voortbrengsel verkregen volgens deze werkwijze. |
Country Status (7)
Country | Link |
---|---|
US (1) | US3325882A (xx) |
JP (1) | JPS512792B1 (xx) |
CH (1) | CH454985A (xx) |
DE (1) | DE1640457B1 (xx) |
FR (1) | FR1483570A (xx) |
GB (1) | GB1073910A (xx) |
NL (1) | NL153721B (xx) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3428866A (en) * | 1965-06-23 | 1969-02-18 | Ibm | Solid state device including electrical packaging arrangement with improved electrical connections |
US3433686A (en) * | 1966-01-06 | 1969-03-18 | Ibm | Process of bonding chips in a substrate recess by epitaxial growth of the bonding material |
DE1539692A1 (de) * | 1966-06-23 | 1969-10-16 | Blume & Redecker Gmbh | Umklebevorrichtung fuer Spulen |
US3484534A (en) * | 1966-07-29 | 1969-12-16 | Texas Instruments Inc | Multilead package for a multilead electrical device |
US3461524A (en) * | 1966-11-02 | 1969-08-19 | Bell Telephone Labor Inc | Method for making closely spaced conductive layers |
US3748726A (en) * | 1969-09-24 | 1973-07-31 | Siemens Ag | Method for mounting semiconductor components |
US3753290A (en) * | 1971-09-30 | 1973-08-21 | Tektronix Inc | Electrical connection members for electronic devices and method of making same |
JPS4988563A (xx) * | 1972-12-23 | 1974-08-23 | ||
US3964157A (en) * | 1974-10-31 | 1976-06-22 | Bell Telephone Laboratories, Incorporated | Method of mounting semiconductor chips |
JPS52109289U (xx) * | 1976-02-16 | 1977-08-19 | ||
US4439918A (en) * | 1979-03-12 | 1984-04-03 | Western Electric Co., Inc. | Methods of packaging an electronic device |
US4251852A (en) * | 1979-06-18 | 1981-02-17 | International Business Machines Corporation | Integrated circuit package |
US5237485A (en) * | 1985-04-26 | 1993-08-17 | Sgs Microelettronica S.P.A. | Apparatus and method for improved thermal coupling of a semiconductor package to a cooling plate and increased electrical coupling of package leads on more than one side of the package to a circuit board |
US4774630A (en) * | 1985-09-30 | 1988-09-27 | Microelectronics Center Of North Carolina | Apparatus for mounting a semiconductor chip and making electrical connections thereto |
US4768077A (en) * | 1986-02-20 | 1988-08-30 | Aegis, Inc. | Lead frame having non-conductive tie-bar for use in integrated circuit packages |
GB2202673B (en) * | 1987-03-26 | 1990-11-14 | Haroon Ahmed | The semi-conductor fabrication |
FR2625067A1 (fr) * | 1987-12-22 | 1989-06-23 | Sgs Thomson Microelectronics | Procede pour fixer sur un support un composant electronique et ses contacts |
USRE35385E (en) * | 1988-12-12 | 1996-12-03 | Sgs-Thomson Microelectronics, Sa. | Method for fixing an electronic component and its contacts to a support |
USRE35578E (en) * | 1988-12-12 | 1997-08-12 | Sgs-Thomson Microelectronics, Inc. | Method to install an electronic component and its electrical connections on a support, and product obtained thereby |
JPH02306690A (ja) * | 1989-05-22 | 1990-12-20 | Toshiba Corp | 表面実装用配線基板の製造方法 |
US5605863A (en) * | 1990-08-31 | 1997-02-25 | Texas Instruments Incorporated | Device packaging using heat spreaders and assisted deposition of wire bonds |
DE19914718B4 (de) * | 1999-03-31 | 2006-04-13 | Siemens Ag | Verfahren zum gleichzeitigen Herstellen einer Mehrzahl von Leuchtdiodenelementen mit integrierten Kontakten |
DE19964471B4 (de) * | 1999-03-31 | 2013-02-21 | Osram Ag | Leuchtdiode und Verfahren zur Herstellung einer Mehrzahl von Leuchtdioden |
US6882044B2 (en) * | 2002-05-17 | 2005-04-19 | Agilent Technologies, Inc. | High speed electronic interconnection using a detachable substrate |
US7343758B1 (en) * | 2004-08-09 | 2008-03-18 | Continental Carbonic Products, Inc. | Dry ice compaction method |
DE102006009723A1 (de) * | 2006-03-02 | 2007-09-06 | Siemens Ag | Verfahren zum Herstellen und planaren Kontaktieren einer elektronischen Vorrichtung und entsprechend hergestellte Vorrichtung |
WO2011129130A1 (ja) * | 2010-04-15 | 2011-10-20 | 古河電気工業株式会社 | 基板および基板の製造方法 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3169892A (en) * | 1959-04-08 | 1965-02-16 | Jerome H Lemelson | Method of making a multi-layer electrical circuit |
US3098951A (en) * | 1959-10-29 | 1963-07-23 | Sippican Corp | Weldable circuit cards |
US3235428A (en) * | 1963-04-10 | 1966-02-15 | Bell Telephone Labor Inc | Method of making integrated semiconductor devices |
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0
- FR FR1483570D patent/FR1483570A/fr not_active Expired
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1965
- 1965-06-23 US US466182A patent/US3325882A/en not_active Expired - Lifetime
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1966
- 1966-05-07 DE DE19661640457 patent/DE1640457B1/de active Granted
- 1966-06-07 GB GB25227/66A patent/GB1073910A/en not_active Expired
- 1966-06-10 CH CH845366A patent/CH454985A/de unknown
- 1966-06-22 NL NL666608622A patent/NL153721B/xx not_active IP Right Cessation
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1969
- 1969-10-29 JP JP44086151A patent/JPS512792B1/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPS512792B1 (xx) | 1976-01-28 |
GB1073910A (en) | 1967-06-28 |
CH454985A (de) | 1968-04-30 |
DE1640457B1 (de) | 1970-10-29 |
US3325882A (en) | 1967-06-20 |
FR1483570A (xx) | 1967-09-06 |
NL6608622A (xx) | 1966-12-27 |
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