NL1035771A1 - Lithographic Method and Method for Testing a Lithographic Apparatus. - Google Patents

Lithographic Method and Method for Testing a Lithographic Apparatus. Download PDF

Info

Publication number
NL1035771A1
NL1035771A1 NL1035771A NL1035771A NL1035771A1 NL 1035771 A1 NL1035771 A1 NL 1035771A1 NL 1035771 A NL1035771 A NL 1035771A NL 1035771 A NL1035771 A NL 1035771A NL 1035771 A1 NL1035771 A1 NL 1035771A1
Authority
NL
Netherlands
Prior art keywords
pattern
substrate
layer
photoresist
barc
Prior art date
Application number
NL1035771A
Other languages
English (en)
Inventor
Eddy Cornelis Antonius Van Der Heijden
Johannes Anna Quaedackers
Dorothea Maria Christina Oorschot
Hieronymus Johannus Christiaan Meessen
Yin Fong Choi
Original Assignee
Asml Netherlands Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asml Netherlands Bv filed Critical Asml Netherlands Bv
Publication of NL1035771A1 publication Critical patent/NL1035771A1/nl

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338Process specially adapted to improve the resolution of the mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

Lithographic Method and Method for Testing a Lithographic Apparatus
FIELD
The present invention relates to a lithographic method.
BACKGROUND A lithographic apparatus is a machine that applies a desired pattern onto a target portion of a substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In that circumstance, a patterning device, which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising part of, one or several dies) on a substrate (e.g. a silicon wafer) that has a layer of radiation-sensitive material (resist). In general, a single substrate will contain a network of adjacent target portions that are successively exposed. Known lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion in one go, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the beam in a given direction (the "scanning"-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction.
There is a continuing desire to be able to generate patterns with finer resolution. In general, shorter wavelength radiation may be used in order to achieve a finer resolution pattern.
One method for providing patterns with increased resolution is dual trench patterning where a first pattern of trenches in a hardmask is overlaid by a second interleaved pattern of trenches in the hardmask to provide a final pattern in the hardmask of higher resolution than either the first or second patterns, which is then transferred to a target layer. Figures la to lj show schematically a dual trench patterning method for providing a high resolution pattern. Figure la shows in cross-section a portion of a silicon substrate 2 provided with a target layer 4 of polysilicon material. A hardmask layer 6 is provided on the target layer 4. A first layer of bottom anti-reflective coating (BARC) material 8 is provided on the hardmask layer 6 and a first layer of photoresist 10 is provided on the first layer of BARC material 8. The hardmask layer 6 is typically formed from an oxide material, such as S1O2 or SiON. The photoresist 10 may be any appropriate type of photoresist, such as, but not limited to, positive tone photoresist. A lithographic apparatus, which may for example be of the type shown schematically in Figure 3, is used to expose a pattern in the photoresist 10. The exposed photoresist 10 is then removed using a developer, such as a caustic solution containing hydroxide ions, so that only unexposed photoresist 10 remains. The pattern is then transferred to the BARC material 8 using an appropriate etching process, such as an ion etch.
The resulting structure, shown in Figure lb, comprises four lines 12 which extend perpendicularly to the plane of Figure lb. The full width of each line 12 is three times the width of the space 14 between each pair of lines 12. Only four lines 12 are shown, but it will be appreciated that Figure lb shows only a portion of the substrate 2, and that many more lines 12 may be provided on the substrate 2.
Referring to Figure lc, the pattern formed in the photoresist 10 and BARC layer 8 is transferred to the hardmask layer 6 using a conventional hardmask etching process, such as an ion etch process. Referring to Figure Id, the first patterned BARC layer 8 and photoresist layer 10 are removed and then second layers of BARC 8a and photoresist 10a are provided on the patterned hardmask layer 6 as shown in Figure le. A different pattern is then formed in the second layers of BARC 8a and photoresist 10a such that portions of the existing patterned hardmask 6 are uncovered, as shown in Figure 1 f. These uncovered portions of the hardmask 6 are then removed by a conventional etch process to yield the structure shown in Figure 1 g.
With reference to Figure lh, the second BARC 8a and photoresist 10a layers are then removed using a conventional method to leave just the patterned hardmask 6 atop the polysilicon target layer 4. As shown in Figure li, further etching (for example reactive ion etching (RIE)) is used to etch the complete high resolution pattern into the target layer 4. Once this has been done, the residual hardmask 6 is removed, for example using etching, to yield the final structure shown in Figure lj.
SUMMARY
The process described above may suffer from a patterning error resulting from one or more different components of the lithographic apparatus, including the patterning device, and/or the method by which the pattern is provided in the various layers of material provided on the substrate. The latter issue is related in part to the different topography of the first and second layers of resist and BARC material. While the first pattern is provided in substantially flat, uniform layers of resist and BARC material provided on a substantially flat hardmask layer, the second pattern is provided in second, less uniform, layers of resist and BARC material deposited on the hardmask layer which now carries the first pattern. Moreover, hi^i temperature deposition of the hardmask layer initially can induce stress in the target and/or substrate layers which may then be relieved by partially removing the hardmask during the first patterning step. As a result, the target and/or substrate layers may deform between the first and second patterning steps, which may lead to pattern overlay errors. Difficulties may therefore be encountered in a high resolution patterning procedure, such as the procedure described above, which results in pattern overlay errors and a consequent loss in patterning accuracy and resolution.
There is a desire to use an alternative technique to achieve patterns with increased resolution. To this end, there is a desire to be able to assess the degree to which the lithographic apparatus contributes to patterning errors, which is, as far as possible, independent of the particular patterning process employed.
According to an aspect of the invention, there is provided a method for providing a pattern on a substrate, the method comprising: providing a first pattern in a first layer of photoresist and a first layer of a first bottom anti-reflective coating material on the substrate; etching the first pattern into the substrate; providing a second layer of photoresist and a second layer of a second bottom anti-reflective coating material on the substrate; providing a second pattern in the second layers of photoresist and the second bottom anti-reflective coating material; and etching the second pattern into the substrate, the first and second patterns on the substrate together defining the pattern.
According to a further aspect of the invention, there is provided a method for testing patterning accuracy of a lithographic apparatus, the method comprising: providing a first pattern in a first layer of photoresist and a first layer of a first bottom anti-reflective coating material on a substrate; etching the first pattern into the substrate; providing a second layer of photoresist and a second layer of a second bottom anti-reflective coating material on the substrate; providing a second pattern in the second layers of photoresist and second bottom anti-reflective coating material; etching the second pattern into the substrate, the first and second patterns on the substrate together defining a test pattern on the substrate; and analyzing the test pattern provided on the substrate to test the patterning accuracy of the lithographic apparatus.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which: - Figures la to lj show schematically a lithographic method; - Figures 2a to 2k show schematically a lithographic method according to an embodiment of the invention; and - Figure 3 depicts schematically a lithographic apparatus which can be used in a method according to an embodiment of the invention.
DETAILED DESCRIPTION
Figures 2a to 2k show schematically a dual-line, double patterning method for providing a high resolution pattern in a substrate 2, e.g., a silicon substrate. The patterned substrate can be used to test the fidelity or accuracy of the patterning process by subsequent analysis of the final pattern formed in the substrate 2.
Figure 2a shows in cross-section a portion of a substrate 2 provided with a layer of a first bottom anti-reflective coating (BARC) material 8 and photoresist 10. In an embodiment, the BARC material is an organic BARC material and may be any suitable organic BARC material 8 such as, but not limited to, Brewer Science's ARC29 BARC material. The BARC material 8 may be deposited so as to provide a BARC layer 8 of any appropriate thickness, for example the BARC layer 8 may have a thickness of at least around 35 nm, although a thicker layer of BARC material 8 may be provided. The photoresist 10 may be, for example, a positive tone photoresist, although any appropriate type of photoresist can be used. The photoresist 10 may be selected to be sensitive to radiation at for example, 193 nm or 248 run A lithographic apparatus, which may for example be of the type shown schematically in Figure 3, is used to expose a pattern in the photoresist 10. The exposed photoresist 10 is then removed using a developer, such as a caustic solution containing hydroxide ions, so that only unexposed photoresist 10 remains, as shown in Figure 2b.
The pattern is then transferred to the BARC material 8 using an appropriate etching process, such as an ion etch, to provide the structure shown in Figure 2c. The BARC 8 etching process may, for example, employ a plasma comprising argon, oxygen and chlorine (which may involve a slight over etch of the pattern features to ensure that that no material is left in between patterned features that might act as a micro mask during the substrate etch) to both open the BARC layer 8 and trim the patterned features to the desired width. The BARC 8 etching process may be carried out using any convenient instrument, for example, a Hitachi 711M instrument. The pattern formed in the photoresist layer 10 and BARC layer 8 shown in Figure 2c comprises four lines 12 that extend perpendicularly to the plane of Figure 2c. The full width of each line 12 is one-third the width of the space 14 between each pair of lines 12. Only four lines 12 are shown, but it will be appreciated that Figure 2c shows only a portion of the substrate 2, and that many more lines 12 may be provided on the substrate 2.
Referring to Figure 2d, the pattern formed in the photoresist 10 and BARC layer 8 is transferred directly to the substrate 2 using any appropriate silicon etch process, such as reactive ion etching (RIE). The silicon etch process may employ a native oxide etch using a plasma comprising chlorine and hydrogen bromide and a plasma comprising oxygen, chlorine and hydrogen bromide, although any appropriate plasma may be used. Any convenient instrument may be used to carryout the silicon etching process, e.g. a Hitachi 711M instrument.
The plasma that is present during the silicon etch process generates a polymeric material comprising photoresist 10, BARC 8 and silicon halogen compounds which are deposited as a protective polymeric layer 16 along the sidewalls of the patterned stacks incorporating layers of photoresist 10, BARC 8 and substrate 2.
The photoresist 10 and BARC 8 layers are subsequently removed using any appropriate method, for example a solvent base strip or a sulfuric acid peroxide mixture (SPM) strip. A further example is ashing. One non-limiting example of a suitable ashing process employs a plasma comprising oxygen, nitrogen and hydrogen and heating the substrate 2 carrying the patterned photoresist 10 and BARC 8 layers by means of radiation to an elevated temperature, for example a temperature of at least around 200 °C, of at least around 250 °C, or of around 270 °C. Any suitable instrument can be used to carry out the ashing process, e.g. an AXCELIS ES3 instrument. This process does not remove the polymeric sidewall layers 16, which, due to a lack of physical support, collapse towards the exposed uppermost surface of the features formed in the substrate 2, as shown in Figure 2e, so as to provide further protective polymeric layers 18. Referring to Figure 2f, new layers of a second BARC material 8a and photoresist 10a are provided on the patterned substrate 2 carrying its protective polymeric layers 16,18. Any suitable BARC material 8 a may be used, for example, but not limited to, an organic BARC material such as Brewer Science ARC29 BARC. The BARC material 8a may be deposited so as to provide a BARC layer 8a of any appropriate thickness. A desired thickness of the BARC layer 8a depends upon various factors, such as the nature of the photoresist 10a, the substrate 2 and the settings of the lithographic apparatus. The BARC layer 8a may have a thickness of at least around 35 nm. Desirably a thicker layer of BARC material 8a is deposited so as to provide the new layer of BARC material 8a with an upper surface that is as flat as possible and thereby level the topography of the BARC layer 8a, which may contribute to patterning accuracy. For example, the BARC layer 8a may have a thickness of at least around 50 nm, at least around 60 nm or at least around 70 nm. Furthermore, the BARC material 8a may be provided so as to provide a layer of BARC material 8a that is around 40 to 100 nm in thickness, around 55 to 90 nm in thickness, or around 65 to 90 nm in thickness. A desired thickness for the BARC layer 8a is around 85 nm. A second pattern is then formed in the new layers of photoresist 10a (see Figure 2g) and BARC 8a (see Figure 2h), via, for example, exposure of the photoresist 10a, development of the photoresist 10a, and etching of the BARC 8a, to provide a second set of lines 20 in the space 14 between the first set of lines 12, in this way the first and second sets of patterned lines 12, 20 may be considered as being interleaved. The photoresist 10a may be patterned in any convenient way, for example, the same method may be used to form the second pattern as was used to form the first pattern in the photoresist layer 10 described above. The BARC 8 etching process may, by way of example only, employ a plasma comprising argon, oxygen and chlorine (which may involve a slight over etch of the pattern features to ensure that that no material is left in between patterned features that might act as a micro mask during the substrate etch) to both open the BARC layer 8 a and trim the patterned features to the desired width. The BARC 8a etching process may be carried out using, for example, a Hitachi 711M instrument. Each second line 20 may be the same width as each first line 12 and each second line 20 may be provided in the center of the space 14 between each pair of first lines 12. In this way, because the spacing 14 between the first lines 12 was three times the width of each first line 12, and thereby, three times the width of each second line 20, the first and second lines 12,20 may be equal in width and regularly spaced apart by a distance that is equal to the width of each line 12, 20.
The portions of the existing patterned substrate 2 which are not covered by the patterned photoresist 10a, BARC 8a or polymeric layers 16,18 (as shown in Figure 2h) are then removed directly by any appropriate silicon etch process, such as a RIE employing, for example, a native oxide etch using a plasma comprising chlorine and hydrogen bromide and a plasma comprising oxygen, chlorine and hydrogen bromide, to yield the structure shown in Figure 2i. A Hitachi 711M instrument may be used to carry out the silicon etching process, although any suitable instrument can be used. During the silicon etching process, further layers of polymeric material 22 are formed and deposited on the sidewalls of the second set of patterned stacks incorporating layers of photoresist 10a, BARC 8a and substrate 2.
The photoresist and BARC layers 10a, 8a are then removed by any convenient means, such as a solvent base strip, a sulfuric acid peroxide mixture (SPM) strip, or ashing. A non-limiting example of a suitable ashing process employs a plasma comprising oxygen, nitrogen and hydrogen and heating the substrate 2 carrying the patterned photoresist 10a and BARC 8a layers by means of radiation to an elevated temperature, for example a temperature of at least around 200 °C, of at least around 250 °C, or around 270 °C. A non-limiting example of a suitable instrument that can be used to carryout the ashing process is an AXCELIS ES3 instrument. This ashing process causes regions 24 of the polymeric sidewall layers 22 to collapse onto the substrate 2 features to provide the structure shown in Figure 2j.
The protective polymeric layers 16,22, 24 provided on patterned features of the substrate 2 are then removed to yield the final patterned silicon substrate 2 as shown in Figure 2k. A convenient method for removing the protective polymeric layers 16,22, 24 is a wet strip process, for example a hydrofluoric acid strip process, optionally also employing hydrogen peroxide, which may be carried out using, for example, a FS1 Mercury instrument. The substrate 2 now carries a high resolution test pattern that can be analyzed using any conventional means to determine the resolution of the test pattern and the accuracy of the patterning process. In this way, an embodiment of the invention may be used to determine patterning accuracy and overlay characteristics of the lithographic apparatus and thereby used to calibrate an apparatus for use in a high resolution patterning procedure. A method according to an embodiment of the invention may obviate or mitigate at least one or more of the disadvantages associated with the process described in relation to Figures la to lj. A method according to an embodiment of the invention removes the need to use a hardmask material which significantly reduces material costs. The complicated, time consuming and costly processes need to pattern and subsequently remove hardmask materials may therefore no longer be required. One or more problems related to over-etching and under-cutting of features during the patterning process may also be removed which avoids the possibility of such reducing patterning fidelity.
An advantage of a method according to an embodiment of the invention is that one or more of the problems discussed above relating to stress-induced deformation of the substrate layer between the first and second patterning steps may be reduced because of the removal of the hardmask layer. Accordingly, a method according to an embodiment of the invention enables the contribution to patterning errors associated with the lithographic apparatus to be assessed in the absence of any contribution to such errors from the hardmask, which represents a significant advance over methods employing a hardmask.
Figure 3 schematically depicts a lithographic apparatus which can be used in a method according to a particular embodiment of the invention. The apparatus comprises: an illumination system (illuminator) IL to condition a beam PB of radiation (e.g. UV radiation or DUV, such as for example generated by an excimer laser operating at a wavelength of 193 nm or 157 nm, or EUV radiation, such as for example generated by a laser-fired plasma source operating at 13.6 nm). a support structure (e.g. a mask table) MT to support a patterning device (e.g. a mask) MA and connected to first positioning device PM to accurately position the patterning device with respect to item PL; a substrate table (e.g. a wafer table) WT to hold a substrate (e.g. a photoresist-coated wafer) W and connected to second positioning device P W to accurately position the substrate with respect to item PL; and a projection system (e.g. a refractive projection lens) PL configured to image a pattern imparted to the radiation beam PB by patterning device MA onto a target portion C (e.g. comprising one or more dies) of the substrate W.
As here depicted, the apparatus is of a transmissive type (e.g. employing a transmissive mask). Alternatively, the apparatus may be of a reflective type (e.g. employing a programmable mirror array of a type as referred to above).
The illuminator IL receives a beam of radiation from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example when the source is an excimer laser. In such cases, the source is not considered to form part of the lithographic apparatus and the radiation beam is passed from the source SO to the illuminator IL with the aid of a beam delivery system BD comprising for example suitable directing mirrors and/or a beam expander. In other cases the source may be integral part of the apparatus, for example when the source is a mercury lamp. The source SO and the illuminator IL, together with the beam delivery system BD if required, may be referred to as a radiation system.
The illuminator IL may comprise adjusting means AM for adjusting the angular intensity distribution of the beam. Generally, at least the outer and/or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator can be adjusted. In addition, the illuminator IL generally comprises various other components, such as an integrator IN and a condenser CO. The illuminator provides a conditioned beam of radiation PB, having a desired uniformity and intensity distribution in its cross-section.
The radiation beam PB is incident on the patterning device (e.g. mask) MA, which is held on the support structure MT. Having traversed the patterning device MA, the beam PB passes through the projection system PL, which focuses the beam onto a target portion C of the substrate W. With the aid of the second positioning device PW and position sensor IF (e.g. an interferometric device), the substrate table WT can be moved accurately, e.g. so as to position different target portions C in the path of the beam PB. Similarly, the first positioning device PM and another position sensor (which is not explicitly depicted in Figure 3) can be used to accurately position the patterning device MA with respect to the path of the beam PB, e.g. after mechanical retrieval from a mask library, or during a scan. In general, movement of the object tables MT and WT will be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the positioning device PM and PW. However, in the case of a stepper (as opposed to a scanner) the support structure MT may be connected to a short stroke actuator only, or may be fixed. Patterning device MA and substrate W may be aligned using patterning device alignment marks Ml, M2 and substrate alignment marks PI, P2.
The depicted apparatus can be used in the following preferred modes: 1. In step mode, the support structure MT and the substrate table WT are kept essentially stationary, while an entire pattern imparted to the beam PB is projected onto a target portion C in one go (i.e. a single static exposure). The substrate table WT is then shifted in the X and/or Y direction so that a different target portion C can be exposed. In step mode, the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure. 2. In scan mode, the support structure MT and the substrate table WT are scanned synchronously while a pattern imparted to the beam PB is projected onto a target portion C (i.e. a single dynamic exposure). The velocity and direction of the substrate table WT relative to the support structure MT is determined by the (de-)magnification and image reversal characteristics of the projection system PL. In scan mode, the maximum size of the exposure field limits the width (in the non-scanning direction) of the target portion in a single dynamic exposure, whereas the length of the scanning motion determines the height (in the scanning direction) of the target portion. 3. In another mode, the support structure MT is kept essentially stationary holding a programmable patterning device, and the substrate table WT is moved or scanned while a pattern imparted to the beam PB is projected onto a target portion C. In this mode, generally a pulsed radiation source is employed and the programmable patterning device is updated as required after each movement of the substrate table WT or in between successive radiation pulses during a scan. This mode of operation can be readily applied to maskless lithography that utilizes programmable patterning device, such as a programmable mirror array of a type as referred to above.
Combinations and/or variations on the above described modes of use or entirely different modes of use may also be employed.
The materials used in the examples described above in relation to Figures 1 and 2 are given as examples only. Other materials may be used. Although the described embodiments refer to trenches and lines, an embodiment of the invention may be used to form other structures. Although the apparatus and method described above according to an embodiment of the invention are discussed in relation to providing a test pattern in a substrate which can be analyzed to determine patterning overlay errors, it should be appreciated that the patterning method is applicable to patterning a substrate for any desirable purpose and is not necessarily limited just to providing a pattern for purely analytical purposes.
Where specific reference has been made above to the use of the lithographic apparatus in the manufacture of ICs, but it should be understood that the method described herein may be applied to the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquid-crystal displays (LCDs), thin-film magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms "wafer" or "die" herein may be considered as synonymous with the more general terms "substrate" or "target portion", respectively.
The terms "radiation" and "beam" used herein encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g having a wavelength of 365, 248, 193, 157 or 126 nm) and extreme ultra-violet (EUV) radiation (e.g having a wavelength in the range of 5-20 nm), as well as particle beams, such as ion beams or electron beams.
The term "patterning device" used herein should be broadly interpreted as referring to a device that can be used to impart a radiation beam with a pattern in its cross-section such as to create a pattern in a target portion of the substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate. Generally, the pattern imparted to the radiation beam will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit. A patterning device may be transmissive or reflective. Examples of patterning device include masks, programmable mirror arrays, and programmable LCD panels. Masks are well known in lithography, and include mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incoming radiation beam in different directions; in this manner, the reflected beam is patterned. The support structure holds the patterning device. It holds the patterning device in a way depending on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions, such as for example whether or not the patterning device is held in a vacuum environment. The support can use mechanical clamping, vacuum, or other clamping techniques, for example electrostatic clamping under vacuum conditions. The support structure may be a frame or a table, for example, which may be fixed or movable as required and which may ensure that the patterning device is at a desired position, for example with respect to the projection system. Any use of the terms "reticle" or "mask" herein may be considered synonymous with the more general term "patterning device".
The term "projection system" used herein should be broadly interpreted as encompassing various types of projection system, including refractive optical systems, reflective optical systems, and catadioptric optical systems, as appropriate for example for the exposure radiation being used, or for other factors such as the use of an immersion fluid or the use of a vacuum. Any use of the term "projection lens" herein may be considered as synonymous with the more general term "projection system".
The illumination system may also encompass various types of optical components, including refractive, reflective, and catadioptric optical components for directing shaping, or controlling the beam of radiation, and such components may also be referred to, collectively or singularly, as a "lens".
The lithographic apparatus may be of a type having two (dual stage) or more substrate tables (and/or two or more support structures). In such "multiple stage" machines the additional tables and/or support structures may be used in parallel, or preparatory steps may be carried out on one or more tables and/or support structures while one or more other tables and/or support structures are being used for exposure.
The lithographic apparatus may also be of a type wherein the substrate is immersed in a liquid having a relatively high refractive index, e.g. water, so as to fill a space between the final element of the projection system and the substrate. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems.
While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. The description is not intended to limit the invention.
Aspects of the invention are as set out in the following, numbered clauses:
CLAUSES 1. A method for providing a pattern on a substrate, the method comprising: providing a first pattern in a first layer of photoresist and a first layer of a first bottom anti-reflective coating material on the substrate; etching the first pattern into the substrate; providing a second layer of photoresist and a second layer of a second bottom anti-reflective coating material on the substrate; providing a second pattern in the second layers of photoresist and the second bottom anti-reflective coating material; and etching the second pattern into the substrate, the first and second patterns on the substrate together defining the pattern. 2. The method of clause 1, wherein the first bottom anti-reflective coating material is an organic bottom anti-reflective coating material. 3. The method of clause 1, wherein the second bottom anti-reflective coating material is an organic bottom anti-reflective coating material. 4. The method of any of the clauses 1 to 3, wherein the etching the first pattern and the etching the second pattern are a reactive ion etching. 5. The method of clause 4, wherein the reactive ion etching includes using a plasma comprising oxygen, chlorine and hydrogen bromide. 6. The method of clause 1, including after the etching the first pattern and before the providing the second layer of photoresist and the second layer of a second bottom anti-reflective coating material, a removing of residual photoresist and residual bottom anti-reflective coating material, from the substrate by ashing. 7. The method of clause 1, including after the etching the second pattern a removing of residual photoresist and residual bottom anti-reflective coating material from the substrate by ashing. 8. The method of clause 6 or 7, wherein the ashing comprises using a plasma. 9. The method of clause 8, wherein the plasma comprises oxygen, nitrogen and hydrogen. 10. The method of clause 6 or 7 wherein the ashing comprises heating residual photoresist, or residual bottom anti-reflective coating material, or residual photoresist and the residual bottom anti-reflective coating material, to a temperature selected from the group consisting of at least around 200 °C, at least around 250 °C, and around 270 °C. 11. The method of clause 6 or 7, further including depositing a layer of polymeric material on the substrate. 12. The method of clause 11, further including removing the layer of polymeric material from the substrate by applying a wet strip after the etching the second pattern into the substrate. 13. The method of clause 12, wherein the applying the wet strip comprises applying a hydrofluoric acid stripping process. 14. The method of any of the clauses 1 - 7, wherein the first pattern and the second pattern comprises a series of lines. 15. The method of clause 14, wherein the second pattern is interleaved with the first pattern such that the pattern has a higher resolution than the first pattern or the second pattern. 16. The method of any of the clauses 1 - 7, wherein the substrate comprises a silicon substrate. 17. The method of any of the clauses 1 to 3, wherein the etching the first pattern or the etching the second pattern is a reactive ion etching. 18. The method of any of the clauses 1 to 3, wherein the etching the first pattern or the etching the second pattern includes using a plasma comprising oxygen, chlorine and hydrogen bromide. 19. The method of clause 1, including after the etching the first pattern and before the providing the second layer of photoresist and the second layer of a second bottom anti-reflective coating material, a removing of residual photoresist or residual bottom anti-reflective coating material, from the substrate by ashing. 20. A method for testing patterning accuracy of a lithographic apparatus, the method comprising: providing a first pattern in a first layer of photoresist and a first layer of a first bottom anti-reflective coating material on a substrate; etching the first pattern into the substrate; providing a second layer of photoresist and a second layer of a second bottom anti-reflective coating material on the substrate; providing a second pattern in the second layers of photoresist and the second bottom anti-reflective coating material; etching the second pattern into the substrate, the first and second patterns on the substrate together defining a test pattern on the substrate; and analyzing the test pattern provided on the substrate to test the patterning accuracy of the lithographic apparatus. 21. The method of clause 20, wherein the first or the second bottom anti-reflective coating material is an organic bottom anti-reflective coating material. 22. The method of clause 20, wherein the first pattern, or the second pattern, or the first and second patterns, is etched into the substrate using reactive ion etching.

Claims (2)

1. Werkwijze om een substraat van een patroon te voorzien, omavttende: een aanbrengen van een eerste patroon in een eerste laag van fotoresist en een eerste laag van een eerste bottom anti-reflective coating materiaal op het substraat; een etsen van het eerste patroon in het substraat; een aanbrengen van een tweede laag van fotoresist en een tweede laag van een tweede bottom anti-reflective coating materiaal op het substraat; een aanbrengen van een tweede patroon in de tweede laag van fotoresist en de tweede laag van de tweede bottom anti-reflective coating materiaal; en een etsen van het tweede patroon in het substraat, waarbij het eerste en het tweede patroon tesamen op het substraat het patroon defmieren.
2. Werkwijze om een patroneer nauwkeurigheid van een lithografisch apparaat the testen, de werkwijze omvattende: een aanbrengen van een eerste patroon in een eerste laag van fotoresist en een eerste laag van een eerste bottom anti-reflective coating materiaal op het substraat; een etsen van het eerste patroon in het substraat; een aanbrengen van een tweede laag van fotoresist en een tweede laag van een tweede bottom anti-reflective coating materiaal op het substraat; een aanbrengen van een tweede patroon in de tweede laag van fotoresist en de tweede laag van de tweede bottom anti-reflective coating materiaal; en een etsen van het tweede patroon in het substraat, waarbij het eerste en het tweede patroon tesamen in het substraat een test patroon defmieren; en een analyseren van het test patroon, aangebracht op het substraat, ter bepaling van de patroneer nauwkeurigheid van het lithografisch apparaat.
NL1035771A 2007-08-20 2008-07-30 Lithographic Method and Method for Testing a Lithographic Apparatus. NL1035771A1 (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US93558607P 2007-08-20 2007-08-20
US93558607 2007-08-20

Publications (1)

Publication Number Publication Date
NL1035771A1 true NL1035771A1 (nl) 2009-02-23

Family

ID=40600097

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1035771A NL1035771A1 (nl) 2007-08-20 2008-07-30 Lithographic Method and Method for Testing a Lithographic Apparatus.

Country Status (3)

Country Link
US (1) US8119333B2 (nl)
JP (1) JP4800354B2 (nl)
NL (1) NL1035771A1 (nl)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090104566A1 (en) * 2007-10-19 2009-04-23 International Business Machines Corporation Process of multiple exposures with spin castable film
US8158334B2 (en) * 2008-01-14 2012-04-17 International Business Machines Corporation Methods for forming a composite pattern including printed resolution assist features
US7883829B2 (en) * 2008-08-01 2011-02-08 International Business Machines Corporation Lithography for pitch reduction
JP2011066120A (ja) * 2009-09-16 2011-03-31 Toppan Printing Co Ltd パターン形成方法およびパターン形成体
US8502324B2 (en) 2009-10-19 2013-08-06 Freescale Semiconductor, Inc. Semiconductor wafer having scribe lane alignment marks for reducing crack propagation
WO2019169122A1 (en) * 2018-03-02 2019-09-06 Tokyo Electron Limited Method to transfer patterns to a layer
US11329089B1 (en) 2019-06-07 2022-05-10 Gigajot Technology, Inc. Image sensor with multi-patterned isolation well

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4440230C2 (de) 1993-11-10 1999-03-18 Hyundai Electronics Ind Verfahren zur Bildung feiner Strukturen eines Halbleiterbauelements
KR100223325B1 (ko) * 1995-12-15 1999-10-15 김영환 반도체 장치의 미세패턴 제조방법
JP4251296B2 (ja) 1998-02-09 2009-04-08 株式会社ニコン 測定方法、調整方法、マーク物体、及び検出装置
AU2300099A (en) * 1998-02-09 1999-08-23 Nikon Corporation Method of adjusting position detector
KR20010004612A (ko) * 1999-06-29 2001-01-15 김영환 포토 마스크 및 이를 이용한 반도체 소자의 미세패턴 형성방법
KR100360397B1 (ko) 1999-11-26 2002-11-18 삼성전자 주식회사 레지스트 제거용 조성물 및 이를 이용한 레지스트 제거 방법
JP2001176788A (ja) 1999-12-21 2001-06-29 Hitachi Ltd パターン形成方法および半導体装置
US7037626B2 (en) * 2001-05-18 2006-05-02 Koninklijke Philips Electronics N.V. Lithographic method of manufacturing a device
US6680164B2 (en) * 2001-11-30 2004-01-20 Applied Materials Inc. Solvent free photoresist strip and residue removal processing for post etching of low-k films
US7125645B2 (en) * 2002-04-10 2006-10-24 United Microelectronics Corp. Composite photoresist for pattern transferring
JP2004296930A (ja) 2003-03-27 2004-10-21 Nec Electronics Corp パターン形成方法
US7265056B2 (en) * 2004-01-09 2007-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming novel BARC open for precision critical dimension control
US7288484B1 (en) * 2004-07-13 2007-10-30 Novellus Systems, Inc. Photoresist strip method for low-k dielectrics
US7432172B2 (en) * 2005-01-21 2008-10-07 Tokyo Electron Limited Plasma etching method
US20070018286A1 (en) 2005-07-14 2007-01-25 Asml Netherlands B.V. Substrate, lithographic multiple exposure method, machine readable medium
US7582413B2 (en) 2005-09-26 2009-09-01 Asml Netherlands B.V. Substrate, method of exposing a substrate, machine readable medium
KR100876808B1 (ko) * 2006-07-10 2009-01-07 주식회사 하이닉스반도체 반도체 소자의 패턴 형성 방법
JP2010511915A (ja) 2006-12-06 2010-04-15 フジフィルム・エレクトロニック・マテリアルズ・ユーエスエイ・インコーポレイテッド 二重パターン形成プロセスを利用した装置製造プロセス
KR100886221B1 (ko) * 2007-06-18 2009-02-27 삼성전자주식회사 포토레지스트 패턴 보호막 형성방법 및 이것을 이용한 미세패턴 형성방법

Also Published As

Publication number Publication date
US8119333B2 (en) 2012-02-21
JP2009094481A (ja) 2009-04-30
US20090148796A1 (en) 2009-06-11
JP4800354B2 (ja) 2011-10-26

Similar Documents

Publication Publication Date Title
EP1744211A1 (en) Substrate, lithographic multiple exposure method, machine readable medium
US8029953B2 (en) Lithographic apparatus and device manufacturing method with double exposure overlay control
US8119333B2 (en) Lithographic method
US20070190762A1 (en) Device manufacturing method and computer program product
US7781149B2 (en) Reduced pitch multiple exposure process
WO2009156225A1 (en) Overlay measurement apparatus, lithographic apparatus, and device manufacturing method using such overlay measurement apparatus
US20110273685A1 (en) Production of an alignment mark
US8980724B2 (en) Alignment target contrast in a lithographic double patterning process
US8252491B2 (en) Method of forming a marker, substrate having a marker and device manufacturing method
US7616291B2 (en) Lithographic processing cell and device manufacturing method
US20050224724A1 (en) Lithographic apparatus, device manufacturing method and device manufactured thereby
US8017310B2 (en) Lithographic method
US20080160458A1 (en) Lithographic device manufacturing method, lithographic cell, and computer program product
US20060035159A1 (en) Method of providing alignment marks, method of aligning a substrate, device manufacturing method, computer program, and device
US7382438B2 (en) Lithographic apparatus and device manufacturing method
KR20100122441A (ko) 리소그래피 더블 패터닝 공정에서 정렬 타겟 콘트라스트의 개선
US20110310369A1 (en) Lithographic method and apparatus

Legal Events

Date Code Title Description
AD1A A request for search or an international type search has been filed
EDI The registered patent application has been withdrawn