MXPA98006717A - Non-conductive substrate forming a band or panel, on which are formed a plurality of support elements - Google Patents

Abstract

The invention relates to a non-conductive substrate (2) forming a band or panel on which are embodied a plurality of support elements, notably for incorporation into a chip card. One side of the substrate (2) has conductive contact surfaces (6) which lie within an outer contour line (4) that determines the size of one support element. The other side of the substrate (2) has conductive structures (9, 10, 11, 14, 15) which, within the outer contour line (4), form at least contact areas (11) for at least one coil to be contacted and at least one semi-conductor chip. Outside each outer contour line (4) the invention provides for recesses (13) in the substrate (2), through which the connections to the coil of the semi-conductor chip can be accessed for test purposes from the side of the contact surface as long as the support element remains in the band or panel.

Description

NON-CONDUCTOR SUBSTRATE THAT FORM A BAND OR A DIE, ON WHICH A GREAT NUMBER OF ELEMENTS COMES CARRIERS FIELD OF THE INVENTION A carrier element that is separated from a substrate of this type is known from Figures 8 and 9 of European Patent 0 671 705 A2. The carrier element of said place is provided for incorporation into a chip card, which can be operated both by contact through a number of contact surfaces, as well as without contact, through an antenna coil, for example, through transformer coupling.

BACKGROUND OF THE INVENTION The carrier elements for chip cards serve for the mechanical support of the semiconductor chip and present, in addition, the contact surfaces necessary for the contact of the chip. They are used both in purely contact chip cards, so that an access to the semiconductor chip is only possible through the contact surface, as well as in the so-called combined cards, in which a non-contact access via ties is also possible. drivers on the card and / or the carrier element or the chip. For this purpose, the conductive loops are connected with coil connections of the semiconductor chip. These carrier elements are not usually produced individually, but on a long strip or a large surface die-cut of a non-conductive material, in large numbers of pieces. This band or punching (hereinafter referred to as substrate) is first structured by, for example, die-cutting recesses and then lined on the one hand with a copper film, which is then structured, for example, by corrosion, so that the contact surfaces for the carrier elements are formed. All conductive structures are electrically conductively connected to each other through narrow lines, in order to perform a galvanic refinement of the surface. The semiconductor chips are fixed to the side opposite the contact surfaces of the substrate and are electrically connected to the contact surfaces by connecting wires through the recesses. Before a functional test of the semiconductor chip, which is still carried out in the band or die, the narrow lines are separated by punching, so that the contact surfaces are electrically isolated from each other. In the carrier element of European Patent EP 0 671 705 A2, the coil connections of the semiconductor chip, through recesses through the substrate, are joined to the contact surfaces on the side opposite the chip of the substrate. The ends of an antenna coil to be connected are also connected to these contact surfaces, passing through recesses provided for this purpose through the substrate, with two of said contact surfaces. The contact surfaces serve, therefore, as connecting elements between coil and semiconductor chip. However, the above has the disadvantage that the coil connections of the semiconductor chip are accessible coming from the side of the contact surface, even after the carrier elements have been separated.

OBJECTS AND ADVANTAGES OF THE INVENTION The task of the present invention is, therefore, to provide a carrier element that is manufactured on a substrate, in which the coil connections of a semiconductor chip to be mounted are accessible coming from the side of the surface of contact, while the carrier element is still in the band or the die and after separating the elements, this possibility of access that prevented. According to claim 1, the task is achieved by means of carrier elements on a non-conductive, metal-lined substrate, in the form of a band or die, in which also the second side of the substrate is provided with conductive structures, which within the The outer contour line of the carrier element forms at least contact elements for at least one coil to be contacted and at least one semiconductor chip, and in which out of the outer contour line there are recesses in the substrate, through which, for testing purposes, access to the coil connections of the semiconductor chip is possible, coming from the contact surface side , while the carrier element is still in the band or in the die. In this way it is possible to test the semiconductor chip, as long as the carrier element has not separated from the band or the die. The recesses in the substrate allow access to the chip side of the substrate, coming from the side of the contact surface. However, when the carrier element is separated from the band or the die, the recesses are no longer part of the carrier element, since they are outside its external contour. Thus, in the individual carrier elements it is no longer possible to access the coil connections of the semiconductor chip, coming from the side of the contact surface. When the carrier element is integrated in a card and, thus, an access to the coil connections is only possible without contact through the connected antenna, coming from the side of the contact surface, it can not be read or affected, or, have electrical access or manipulate the data transfer without contact. In order to configure the test access to the coil connections of the semiconductor chip as simple as possible, advantageously the recesses can be covered with conductive surfaces, which are connected to the conductive structures with which the semiconductor chip (s) are connected and the reels) . The test tips can be placed on the surface, simply, through the recesses. Another method provides for covering the recesses on the side of the contact surface of the substrate, with a conductive surface, which is connected to the conductive structures on the chip side of the substrate through contacts passing through the recesses. The contacts that pass through can completely fill the recesses or only cover their walls.

BRIEF DESCRIPTION OF THE FIGURES Below, the invention is illustrated in more detail based on an example of embodiment with the help of the figures. Figure 1 is the front side of a section of a substrate web. And Figure 2 is the rear view of a section of a substrate band.

DETAILED DESCRIPTION OF THE INVENTION Figure 1 is a section of a band 1, in which four carrier elements are formed by pairs. However, it is possible to arrange a greater number than two contiguous carrier elements on the band. It consists of a non-conductive substrate 2, which can be used as a material, for example, epoxy resin reinforced with glass fiber. The substrate 2 has perforations 3 along both edges, which serve for transport by haulers that are introduced into the perforations 3, for example, when assembling in the band semiconductor chips or in the test run. The external contour of a carrier element is indicated by a dotted line 4. The carrier elements already with the assembled elements are punched or otherwise separated from the web 1 along this line 4. The non-conductive substrate 2 was lined with a metal film, preferably a copper film. Next, the metal film was structured by corrosion, so that contact surfaces 5 were formed within the outer contour line of the carrier elements 4, as well as other contact surfaces 6 that are outside the outer contour line. 4 of the carrier element. The contact surfaces 5, 6 are connected through narrow lines 7 with the lines running around the outer contour lines 4, and thus, they are all connected to each other. This electrical short circuit is necessary, since the contact surfaces 5, 6 are galvanically refined on their surface. Figure 2 is the other side of the substrate 2 on which the semiconductor chip (not shown) is mounted. Also this side is provided with conductive structures 9, 10, 11, 14, 15 which were formed by the lining with metal and corrosion films. The substrate was first lined on one side with a metal film and then provided with recesses 12, 13, which are formed, for example, by punching. For the next corrosion of the conductive structures 9, 10, 14, 15, the recesses 12 must be covered, so that metallic zones 11 are left around them, which can be used for contacting the coil connections of a semiconductor chip . The metallic zones 11 form closed conductive rings, respectively, around the recesses 12. In order to avoid the losses due to eddy currents that eventually appear, interruptions can also be foreseen. Of the recesses 12, 13, the first recesses 12 are inside the external contour line 4 and serve for the electrical connection of the semiconductor chip with the contact surfaces 5 to the other side of the substrate 2, through joining wires. The second recesses 13 are made as traversing contacts, which connect the other contact surfaces 6 by lines 14 with the connecting contact surfaces of reels 10. The substrate 4 is relatively flexible. In a chip card, a semiconductor chip mounted therein would be subjected to considerable bending loads. The larger chips would even break. For this reason, on the chip side of the carrier element a reinforcement frame (not shown) is glued with insulating glue. The reinforcing frame is preferably made of metal, but can also be of another material. Since the carrier elements are normally glued to the chip card, there must be space for the adhesive along the edge of the carrier elements, so that the reinforcement frame passes only slightly outside the area of the connecting perforations. 12. As well, the interior of the reinforcement frame, to protect the semiconductor chip (s) and the junction wires, is filled with a filling mass, the contact surfaces 10 for the connection of an antenna coil for the Non-contact operation of the semiconductor chip, must be outside the reinforcement frame. On the other hand, conductive structures 15 must be provided, which run under the frame inwardly to join the semiconductor chip. Since the frame would be unstable on these conductive structures 15, under the reinforcement frame, on the substrate 2, a metallized zone 9 is provided that matches the shape of the frame, at least of the same thickness as the conductive structures 15. Like this metallization ring 9 and also the contact boxes 11 within the frame, with which the coil connections of the semiconductor chip are joined by connecting wires and then connected through the conductive structures 15 with the contact surfaces of the connection of coils 10, constitute parasitic capacities, its surface is chosen as small as possible, to keep the capacity as small as possible. The metallization ring 9 under the reinforcing frame must not be closed, otherwise the ends of the coil would be short-circuited. However, in this way additional parasitic capacities are formed between the open ends of the metallization ring 9 and the line (s) 15. In order to keep these capacities as low as possible, the separation in the metallization ring under the frame, On the one hand, it must be designed as large as possible, but on the other only so large that the filling mass can not escape under the frame. The finished semiconductor chips assemble and unite on the band or the punch, before separating them, are tested on the band or the punching. As, however, all contact surfaces 5, 6 are electrically connected to each other through narrow lines 7 and 8, said lines must first be separated. The above is done by punching holes 16. For reasons of clarity, said holes are only shown on a carrier element in Figures 1 and 2. The semiconductor chip can be tested on a chip card, as in normal operation, through the contact surfaces 5. The contactless operation, according to the invention, can be tested starting from the side of the contact surface, passing through the other contact surfaces 6, which are joined by the contacts passing through 13 and the lines 14 with the contact surfaces of the coil connection 10. After separating the carrier elements, the lines 14 are interrupted and the contacts traversing 13 and the other contact surfaces 6 are not part of a carrier element, so that already access from the contact side of the carrier element to the coil connections of the semiconductor chip is not possible. Furthermore, in a carrier element used in a chip card, an access to the coil connections is only possible through a connected antenna coil. In order to be able to test the coil connections from the contact side, the other contact surfaces 6 are not indispensable. It would be sufficient to fill the recesses with conductive material. However, the surface to be contacted by the test tips would be markedly smaller. Another possibility consists in not making the recesses 13 as contacts that pass through, but instead of the above, covering them on the chip side with contact surfaces. The test tips could then be brought into contact with these contact surfaces through the recesses 13. However, all the variants of embodiment have in common that an access to the coil connections of the semiconductor chip from the the contact surfaces, is only possible as long as the carrier element has not been separated, but to remain part of a band or a die-cut.

Claims (4)

NOVELTY OF THE INVENTION Having described the foregoing invention, it is considered a novelty, and therefore, the content of the following is claimed as property: CLAIMS

1. A non-conductive substrate forming a strip or a die, in which a large number of carrier elements is formed, in particular for incorporation into a chip card, in which one side of the substrate is provided with conductive contact surfaces, which are inside an outer contour line that determines the size of a carrier element, characterized in that the other side of the substrate is provided with conductive structures, which within the outer contour line form at least contact boxes for at least one coil to contact and at least one semiconductor chip, and because out of each outer contour line there are recesses in the substrate, through which, for testing purposes, it is possible to access the coil connections of the semiconductor chip, from the side of the contact surface, as long as the carrier element remains in the band or in the die.

2. A substrate according to claim 1, characterized in that the recesses are formed as contacts passing through the conductive structures and are respectively connected to a relatively small additional contact surface outside the outer contour line. on the contact surface side.

3. A substrate according to claim 1, characterized in that on the side opposite the contact surfaces, the recesses are respectively covered by a surface joined to the conductive structures.

4. A substrate according to claim 1, characterized in that the recesses are formed as contacts passing through the conductive structures and are respectively in contact with one of the contact surfaces within the outer contour line .