MXPA00006332A - Test access system and method for digital communication networks - Google Patents

Abstract

The system includes a number of line access devices, each of which is coupled to at least one of the communication lines, both ends of which terminate at telecommunications termination sites. One or more monitoring buses are defined by a number of relays, one or more of which is coupled to one of the line access devices. A test device interface, which is selectively coupled to the bus, provides bi-directional connectivity between the selected communication line and a selected testing device coupled thereto.An activated one or more of the relays couples a selected one of the communication lines to a selected one of the testing devices via the test device interface. One or more signal paths defined as passing through the relays, test device interface, and a portion of the line access devices define untapped point-to-point connections.

Description

TEST ACCESS SYSTEM AND METHOD FOR DIGITAL COMMUNICATION NETWORKS RELATED APPLICATIONS This application claims the benefit of the Provisional Application of the United States of America Number 60 / 068,841, filed on December 24, 1997.

FIELD OF THE INVENTION The present invention relates in general to communication line test systems, and more specifically, it relates to a test system and method that provides for the selective connection of the test equipment with any of a plurality of test lines. high-speed digital communication or any other high-frequency digital transmission lines.

BACKGROUND OF THE INVENTION The term T-l refers to a telecommunications standard for digital transmission used extensively in the United States. The T-l standard provides a transmission link, with a capacity of 1,544 megabits per second (Mbps) over a twisted wire pair. With this capability, a T-l link can handle the equivalent of 24 voice conversations, each digitized at 64 kilobits per second (Kbps). However, with the ever increasing demands that modern technology and the information superhighway place on the communications industry, a growing bandwidth is being demanded. In response to this demand, faster communication links, such as the T-3 transmission links, are being deployed to meet these demands. A conventional T-3 link provides the equivalent of 28 T-l links, or a capacity of 44,736 Mbps, which is equivalent to 672 voice conversations. A T-3 line usually runs on fiber optic, microwave radio, or coaxial cable lines. The signaling protocol for T-3 systems, commonly referred to as DS-3 signaling, involves pulses that require a bandwidth comparable to VHF radio waves (very high frequency). At these frequencies, providing switchable access between the communication links and the test equipment can become problematic, due to the need to ensure the integrity of the signal as the DS-3 pulses propagate through the system. For example, at the circuit level, solid-state switching devices are no longer effective for making switchable connections, due to the parasitic high-frequency circuit paths present in these devices. At the level of the printed circuit board, it becomes necessary that the circuit paths appear substantially as transmission lines, and any failure to do so can result in poor substantial couplings, reflections, and other signal distortions, in addition to noise, on the same circuit board.

SUMMARY OF THE INVENTION It is broadly an object of the present invention to provide a method and apparatus for switching a plurality of test devices between a plurality of transmission links, while preserving the integrity of the signal as it propagates through of the system. It is specifically contemplated that all signal paths in the system exhibit the characteristics of a transmission line that does not provide appreciable attenuation or distortion of the signal, and no appreciable noise. In accordance with a preferred embodiment demonstrating objects, features, and advantages of the present invention, a system is provided for providing selective test access to a plurality of communication signal lines, by a plurality of test devices. The system includes line access cards that provide an interface for a plurality of high frequency signal lines, and at least one test card that provides an interface for a plurality of high frequency test devices. The cards are connected to a motherboard, which provides a selective connection between the test devices and the signal lines. All the trajectories of high frequency signals on the boards and on the motherboard exhibit the characteristics of a transmission line with a previously defined characteristic impedance, and transfer high frequency pulses with minimum attenuation, minimum distortion, and minimal noise. Switching is provided on the motherboard by relays with low insertion and noise loss. The relays are provided on the line access cards, test card, and motherboard. All signal paths represent straight point-to-point electrical circuits without leads. The connections between the back cards of the line access devices and the motherboard are provided by 96-pin DIN connectors, and represent the only part of the high-frequency signal path where the impedance is not strictly controlled. However, the integrity of the signal through these connectors is maintained by implementing an assignment and configuration of peaks of the connector that simulates a coaxial transmission line.

BRIEF DESCRIPTION OF THE DRAWINGS The foregoing and other objects, features, and advantages of the present invention will come to be understood more fully from a detailed description of the currently preferred embodiment, reference being made to the accompanying drawings, in which: Figure 1 is a front perspective view of a test access system in accordance with one embodiment of the present invention. Figure 2 is a rear perspective view of a test access system in accordance with one embodiment of the present invention. Figure 3 is a schematic side view of the motherboard, illustrating the manner in which the front and back cards of a line access module are connected thereto, in accordance with one embodiment of the present invention. Figure 4 is a functional block diagram illustrating the operation of a test access system in accordance with an embodiment of the present invention. Figure 5 is a functional block diagram of a test access system illustrating the architecture of the monitoring busbars, which allow switching access between the subsequent test card and the subsequent line card in accordance with a mode of the present invention. Figure 6 is a schematic block diagram of a backline card of a line access module in accordance with one embodiment of the present invention. Figure 7A is a schematic block diagram of a Type-1 posterior test card in accordance with one embodiment of the present invention. Figure 7B is a schematic block diagram of a Type-2 back test card in accordance with one embodiment of the present invention. Figure 8 is a functional block diagram illustrating the operation of a front line card of a line access module in accordance with one embodiment of the present invention. Figure 9 is a schematic block diagram illustrating the operation of a front test card of a test card module in accordance with an embodiment of the present invention. Figure 10 is a fragmentary sectional view showing a portion of a circuit board, as used in the preferred embodiment of the present invention. Figure 11 is a schematic diagram illustrating a 96-pin connector, as used in the preferred embodiment of the present invention, with a peak configuration designed to achieve an effective transmission line.

DETAILED DESCRIPTION OF THE PREFERRED MODALITY Turning now to the drawings, Figures 1 and 2 are front and rear perspective views, respectively, of a test access system 8 incorporating the objects and features of the present invention. One embodiment of a system that operates in accordance with the principles of the present invention is available from ADC-Hadax, Inc. of South Hackensack, New Jersey, as the '2005 T-3 Access System. "The objects and features of the present invention will generally be described herein in the context of a telecommunication network conforming to a T-3 transmission carrier standard, which is used in North America It is understood that the systems and methods of the present invention are applicable to access and test other types of transmission lines, including high-speed digital transmission lines that provide transmission speeds of the order of tens or hundreds of megabits per second (Mbps). As best seen in Figures 1 and 2, the test access system 8 includes a number of line access cards 15, a test equipment card 35, a control card 25, and dual power supplies 28, 29. Each of the line access cards 15, as can be seen in Figure 2, includes a number of connectors to receive the corresponding connectors of a number of communication lines, such as T-3 transmission lines. The test equipment card 35 includes a number of connectors that receive the corresponding connectors from a number of test devices. The control card 25, which includes a programmable processor or CPU, coordinates the activities of the test access system 8, and furmore can communicate with a remote control unit by means of a communications card 18. In accordance with a preferred embodiment of the present invention, and as illustrated in Figures 1 and 2. The test access system 8 is designed to be modular and rack mountable. According to this embodiment, the test access system 8 includes 9 line access cards 15, each of which comprises a front line card (FLC) 17, and a back line card (RLC) 19. Test equipment card 35, according to this embodiment, comprises a front test card (FTC) 37, and a subsequent test card (RTC) 39. As seen in addition in Figure 3, the test access system 8 includes a two-sided motherboard 10, with front circuit boards 12 connected to the front of the motherboard 10, and rear circuit boards 14U, 14L, connecting to the back of the motherboard 10. Instead of a single board of full-height circuitry, dual half-height circuit boards, such as an upper rear card 14U, and a lower rear card 14L can be provided, as illustrated in Figure 3. In this configuration, nine circuit boards are connected. front line 17 on the front of the motherboard 10. The back of the motherboard 10 provides the coupling for a bank of 9 higher backline cards 19 (i.e., RLC1-RLC17, only numbers only), and a bank of 9 line cards lower rear 19 (RLC2-RLC18), even numbers only), for a total of 18 line access cards 15. Also coupled to the motherboard 10, there is a single test equipment card 35, state the front test card 37 and the subsequent test card 39 of the test equipment card 35 coupled to the front and rear of the motherboard 10, respectively. The control card (C) 25, the communications card (COMC) 18, and each of the power supplies 28, 29, are also connected to the motherboard 10. In operation, four conventional BNC connectors (RXE, RXF , TXE, TXF) provided on each line access card 15, and typically on the back line card 19 of each line access card 15, provide an interface connection for a bidirectional communication line, such as a line of T3 transmission. In a similar manner, the BNC connectors (TXA, TXB, RXA, RXB) provided on the card of the test equipment 35, and usually on the subsequent test card 39 of the card of the test equipment 35, provide a test port double, which allows two pieces of communication line test equipment to be connected to it. The communication card 18 has an interface 20 that includes three connections that provide an RS-232 interface to and from the test access system 8. However, it will be appreciated that any other type of communication interface 20, such as an interphase of network 20, it would work equally well. In accordance with one embodiment of the present invention, the front line card 17 of each line access card 15 provides control to a pair of rear line cards 19. According to this embodiment, the front test card 37 of the test equipment card 35 provides control to the subsequent test card 39. The front lines cards 17 and the front test card 37 operate under the control of the CPU provided in the control card 25. The block diagram of Figure 4 illustrates the way in which the different cards are interconnected through the mother board 10, and the operation of the test access system 8 will be better understood by referring to that block diagram. A duplex communication line is connected to each of the 18 subsequent line cards 19 (ie, RLS1 to RLS18). Two pieces of the communication line test equipment are connected to the subsequent test card 39 (RTC), and are selectively connected to one of the 18 RLCs 19. This is achieved by means of two monitoring busbars, MBl and MB2. . The RTC 39 is connected to both busbars, MBl and MB2, and each RCL 19 is connected to one of the two busbars, MBl, MB2. In the embodiment illustrated in re 4, the 19 (higher) RLCs are connected to MBl, and the 19 (lower) RLCs are connected to MB2. The details for making connections will be discussed further below. At this point, it is sufficient to note that the connection between one of the monitoring busbars, MBl or MB2, and RLC 19, is made through one or more relays. According to the embodiment shown in re 4, each pair of RLCs 19 occupying a common slot (ie, an upper and a lower RLC 19) is controlled by a corresponding front line card 17. The front test card (FTC) 37 of the test equipment card 35 controls the subsequent test card (RTC) 39. The FLCs 17 and FTC 37, in turn, are controlled by the CPU provided in the control card (CC) 25. The control card 25 receives conration commands from a controlling device, such as a terminal or a personal computer, by means of an RS-232 link provided through the communication card (COMC) 18. The communication card 18 may also provide output information through one of its communication ports 20, such as the status information provided by the control card 25. The use of communication links makes remote testing particularly efficient. An important aspect of a test access system 8 in accordance with the present invention involves ensuring the integrity of the signal as the pulses of the communication signals propagate through the test access system 8. To ensure an high level of signal transmission integrity, all signal paths within the test access system 8 are designed to exhibit the characteristics of an unbalanced transmission line, with a characteristic impedance of 75 ohm, capable of transferring signal pulses from communication with minimum attenuation, minimal distortion, and minimal noise. However, it will be appreciated that other impedance characteristics will work equally well, when appropriate. In order to provide this signal transmission integrity at the level of the printed circuit board, special deployment techniques are employed. According to one embodiment of the present invention, the cards of the test access system 8 that are involved in the transfer of information signals (for example, the RLCs 19, RTC 19, and the motherboard 10) are circuit boards printed in multiple layers, with controlled impedance. A circuit board construction according to this embodiment is illustrated in re 10, which shows a section of a circuit board 50 with four layers, layer 1 to layer 4. However, it will be appreciated that an Board of 6 or more layers. All traces that transfer information signals are designed as unbalanced transmission lines with a characteristic impedance of 75 ohms. The transmission lines have a strip conration, consisting of a signal conductor and two reference planes, one above and one below the signal conductor. For maximum electromagnetic induction (EMI) protection, guard conductors are placed on either side of the signal conductors, and surround each signal stroke. The guard conductors are located on the signal layer of a printed circuit board, and are connected to both reference planes at every 1.27 centimeters. The layers 1 to 3 illustrated in Figure 10 define the fringe configuration, with the path of the high frequency signal (HF) provided in the layer 2 by the conductor 52. The guard conductors 54, 54 are also provided in the layer 2, on either side of the signal conductor 52. Layer 4 is used for the relatively low speed (control) logic signals. The substrate material of the printed circuit board is preferably FR-4.

The components used in the test access system 8 are also selected to have a characteristic impedance of 75 ohms, and excellent frequency characteristics. The input and output connections for the information signal paths are provided by 75 ohm BNC connectors mounted on the printed circuit board. Switching is provided by 75 ohms high frequency relays with low insertion and noise loss. The connections between the subsequent cards (RLCs, RTC) 19, 39, and the motherboard 10, are provided by 96-pin DIN connectors. The interface of the DIN connector represents the only part of the path of the information signal where the impedance is not strictly controlled. However, the integrity of the signal through these connectors is maintained using a peak allocation that simulates a coaxial transmission line, thereby minimizing discontinuity, and making the connector effectively transparent to the information signal that is present. spreading This peak assignment makes use of a peak from Column B (ie, average column of peaks) of the connector, as a signal conductor, and the surrounding 8 peaks are used as protection conductors. In Figure 11 a connector 60 is illustrated incorporating this peak configuration, where four separate peak arrays are shown. For example, the average peak of row 31 is shown connected to the signal conductor. At the same time, the remaining peaks of rows 30-32 are connected together and to the ground plane. From the point of view of the design of the electrical circuit, all the signal paths are straight electric circuits from point to point without derivations. All the connections between the different signal paths in the RLCs 19 and in the RTC 39, are made through relay contacts. In RLCs 19, the paths of "normal traversed" signals are derived to monitor through 750 ohm bridge resistors, which virtually eliminate any effect of branch circuits on the communication lines in the monitoring modes. As discussed above, the RLCs 19 are connected to the monitoring busbars, MBl and MB2, through the relays located on the motherboard 10, and are controlled by the RLCs 17. Figure 5 is a diagram of Schematic blocks useful in explaining the manner in which switching of the monitoring busbar is achieved in a test access system 8 of the present invention, to ensure the integrity of the signal. Figure 5 includes components that have already been shown and discussed with respect to Figure 4, and these components are represented by similar reference characters. Figure 5 illustrates, in particular, the relays, which are illustrated as switches, that achieve the switching of the monitoring busbar. The RTC, SWO relays, which are part of the RTC 39 in one mode, are capable of connecting the RTC 39 to any MBl or MB2, depending on the position of the SWO. With respect to the monitoring busbars, MB1 and MB2, each RLC 19 includes a corresponding set of relays. By way of example, the upper RLCs 19 (odd numbers) are coupled to the associated relay sets SWl-SWl7. In each case, these relays are normally in their downward position (ie, when they are not energized). When there are no energized RLC relays, end-to-end continuity is provided for each monitoring busbar, MBl, MB2, and no RLCs 19 are connected to the monitoring busbars. However, the relays of the RLCs 19 are activated one at a time, to put the RLCs 19 in the corresponding monitoring busbar. When a set of relays is energized in this way for a particular RLC 19, the relays are placed essentially in the upward position with respect to the illustration of Figure 5., which interrupts the end-to-end continuity of the corresponding monitoring bus, and connects the corresponding RLC 19 to that monitoring bus. The described construction of the motherboard 10 ensures that, at any time, there is only one point-to-point connection between the RTC 39 and the selected RLC 19, and no other RLCs 19 are connected to the monitoring busbar. At the same time, the part of the monitoring bus that is not being used is disconnected, and does not interfere with the propagation of the signal. Figure 6 is a schematic block diagram of a backline card (RLC) 19, in accordance with one embodiment of the present invention. In general, the RLC 19 includes two interfaces: one with the communication line, and one with the motherboard 10. The interface with the communication line is provided by four BNC connectors. The interface with the mother board 10 is provided by a 96-pin female DIN connector. The RLC 19 shown in Figure 6 includes a double communication port with two inputs (RXE and RXF) and two outputs (TXE and TXF). The RLC 19 also includes a plurality of relays, which are represented as switches in Figure 6, which are operated under the control of the corresponding FLC 17. There are two "normal-traversed" paths, that is, from RXE to PXF, and from RXF to TXE. The RLC 19 also provides four paths to a monitoring busbar. Two of the trajectories, from M0N_TXE to TXE, and from MON_TXF to TXF, are direct trajectories. The other two trajectories are from RXE to MON_RXE, and from RXF to MON_RXF, and can be direct trajectories, or paths traversed B or B & amp;; T, depending on the desired test mode. Each RLC 19 has the capability to provide backclock connections to the communication port, from RXE to TXE, and from RXF to TXF. It should be noted that, in a preferred embodiment, two backline cards 19 (upper and lower) are used in each slot. This configuration has the advantage that, in the case that it is necessary to replace a line card, only one line must be temporarily put out of service. It will be appreciated that a single line card accommodating two lines of duplex communication can also be employed. The subsequent test card (RTC) 39 is preferably provided in two types. Figures 7A and 7B are schematic block diagrams of a Type 1 PSTN, and a Type 2 PST, respectively. Both types of RTC include a double test port with two inputs (RXA and RXB) and two outputs (TXA and TXB). Each RTC 39 also includes a plurality of relays, illustrated as switches, that are operated under the control of a front test card (FTC) 37. The RTC 39 Type 1, shown in Figure 7A, can provide retrocycle for many of the tickets any of the exits. The RTC 39 Type 2, shown in Figure 7B, can provide retrocycle from RXA to TXA, and from RXB to TXB only. On the other hand, the Type 1 RTC can not provide backcross on the unused port when the modes of Division A, Division AX, Division B, and Division BX are selected. Four connectors marked with NR in Figures 7A and 7B provide connection to the following grid assembly in the "daisy chain" configurations. Depending on the position of the contacts of the "daisy chain" shown in Figures 7A and 7B, the test port can be connected with either one of the monitoring busbars of the present grid assembly, or the following assembly of grate. The "crossed" contacts provide direct or cross connections for the inputs (RXA, RXB) and for the outputs (TXA, TXB). The "retrocycle" contacts provide retrocycle connections from RXA to TXA, and from RXB to TXB. The "MON Bar Selection" contacts provide connections to either of the two monitoring busbars, MBl, MB2. The RTC 39 includes three interfaces: one with the test equipment of the communication line; one with the following grid assembly; and one with the motherboard 10. The interface with the test equipment of the communication line is provided by four BNC connectors, such as RXA, TXA, RXB, and TXB shown in Figure 2. The interface with the following assembly of grid is provided by four BNC connectors marked with "next grid", which are also shown in Figure 2. The interface with the mother board 10 is provided by a 96-pin female DIN connector.

Figure 8 is a functional block diagram illustrating the operation of a front line card (FLC) 17 in accordance with one embodiment of the present invention. For purposes of illustration, and not limitation, there is shown an FLC 17 coupled with a pair of subsequent line cards 19, RLC1 and RLC2, each of which is controlled by the FLC 17. In turn, the FLC 17 is controlled by a CPU provided on the control card 25. The FLC 17 includes two control blocks (CTRL1 and CTRL2), each of which provides control for a respective RLC 19 (RLC1 and RLC2, respectively). The FLC 17 further includes a set of relays to define part of a respective monitoring bar, MB1, MB2. Two light emitting diodes (LED1 and LED2) provided on the front of the FLC 17, indicate the status of the corresponding RLCs 19. By way of example, when a respective RLC 19 is in a test mode, the corresponding LED illuminates, whereas when a retrocycle mode is selected, the corresponding LED flashes. In addition to the relay drives, the control blocks CTRL1 and CTRL2 also include two 8-bit control registers. Registrars 1 and 2 are provided in CTRL1 for RCL1, and registers 3 and 4 are provided in CTRL2 for RLC2. The bits of the odd recorders (Recorder 1 and Recorder 3) have the following effect on the relays of the corresponding RLC 19, according to one embodiment of the present invention: D7: when it is 0, it closes the "normal traversed" path from RXE up to TXF. when it is 1, connect RXE to the monitoring busbar. D6: when it is 0, it closes the "normal traversed" path from RXE to TXF. when it is 1, connect TXF with the monitoring busbar. D5: when it is 0, select the circuit B & T. when it is 1, select the direct connection from RXE to the monitoring busbar. D4: when it is 0, select the split mode. when it is 1, select the monitoring mode. D3: when it is 0, it closes the "normal traversed" path from RXF to TXE. when it is 1, connect RXF to the monitoring busbar. D2: when it is 0, select the circuit B & T. when it is 1, select the direct connection from RXF to the monitoring busbar. DI: when it is 0, select the split mode. when it is 1, select the monitoring mode. DO: when it is 0, it closes the "normal traversed" path from RXF to TXE. when it is 1, connect TXE to the monitoring busbar. In a similar manner, the peer control registers (Recorders 2 and 4) have 8 bits that have the following effect on the relays of the corresponding RLC 19 in accordance with one embodiment of the present invention: D7: when it is 0, disconnect MON_RXE and MON_TXF of the RLC. when it is 1, it connects M0N_RXE and M0N_TXF to the RLC. D6: when it is 0, disconnect M0N_RXF and MON TXE from the RLC. when it is 1, it connects M0N_RXF and MON_TXE to the RLC. D5: when it is 0, deselects the retrocycle from RXE to TXE. when it is 1, select the retrocycle from RXE to TXE. D4: when it is 0, select the retrocycle from RXF to TXF. when it is 1, deselects the retrocycle from RXF to TXF. D3: when it is 0, it disconnects the protector of the switching circuit RXE-TXF from the monitoring bus guard. when it is 1, it connects the protector of the switching circuit RXE-TXF to the guard of the monitoring busbar.

D2: when it is 0, it disconnects the protector of the switching circuit RXF-TXE from the monitoring bus guard. when it is 1, it connects the protector of the switching circuit RXF-TXE to the guard of the monitoring busbar. DI: when it is 0, it disconnects the protector of the switching circuit RXE-TXF from the protector of the switching circuit RXF-TXE. when it is 1, it connects the protector of the switching circuit RXE-TXF to the protector of the switching circuit RXF-TXE. DO: when it is 0, turn off the LED for the corresponding RLC. when it is 1, it illuminates the LED for the corresponding RLC. It will be appreciated that the control registers CNRL1 and CNRL2 of the RLC 19 allow a large number of different modes of operation, by virtue of the different 8-bit words that can be provided in each register. Table 1 provided below exemplifies a number of different modes of operation that may be available for each RLC 19. The modes described correspond to different test modes defined by Bellcore standards for test communication equipment.

TABLE 1 TABLE 1 (Continued) Figure 9 is a schematic block diagram illustrating the operation of a front test card (FTC) 37, in accordance with one embodiment of the present invention. The FTC 37 controls the relays of the subsequent test card (RTC) 39, and it is itself controlled by the CPU provided in the control card 25. The FTC 37 includes a single control block (CTRL1) provides control to the RTC 39. A light emitting diode (LED) on the front of 1 FTC 37, indicates the status of the RTC 39. When the RTC 39 is in a test mode, the LED is illuminated, whereas when the RTC 39 is in a retrocycle mode, the LED flashes. The FTC 37 contains relay drives for the RTC 39, and two 8-bit controllers. The bits of the CTRL1 Control Recorder 1 in the FTC 37 have the following effect on the relays of the RTC 39, in accordance with one embodiment of the present invention: D7: when it is 0, it selects the line MON_RXB from the busbar of superior monitoring (MBl). when it is 1, select the MON_RXB line from the lower monitoring busbar (MB2). D6: when it is 0, deselects the retrocycle between RXB-TXB (if the crossing is not active). when it is 1, select the retrocycle between RXB-TXB (if the crossing is not active). D5: not used.

D4: not used. D3: when it is 0, select the MON_TXA line from the upper monitoring bar (MBl). when it is 1, select the MON_TXA line from the lower monitoring busbar (MB2). D2: when it is 0, select the MON_TXB line from the upper monitoring bar (MBl). when it is 1, select the MON_TXB line from the lower monitoring busbar (MB2). DI: when it is 0, deselect the retrocycle between RXA-TXA (if the crossing is not active). when it is 1, select the retrocycle between RXA-TXA (if the crossing is not active). DO: when it is 0, select direct connections with TXA and TXB (junction). when it is 1, select cross connections with TXA and TXB (junction).

The bits of the control register 2 of CNRL1 in the FTC 37, have the following effect on the relays of the RTC 39, in accordance with an embodiment of the present invention: D7: not used. D6: not used. D5: when it is 0, select the MON_RXA line from the upper monitoring busbar (MBl). when it is 1, select the MON_RXA line from the lower monitoring busbar (MB2). D4: when it is 0, select direct connections with RXA and RXB (junction). when it is 1, it selects cross connections with RXA and RXB (junction). D3: not used. D2: when it is 0, select the local grid. when it is 1, select the next grid. DI: not used. DO: when it is 0, turn off the test LED. when it is 1, it illuminates the test LED.

Accordingly, it will be appreciated that the different bit combinations available in the two CNRLl control registers in FTC 37 will produce a large number of operational modes in the RTC 39. Table 2 provided below exemplifies different operational modes available for the RTC. 39, according to one embodiment of the present invention.

TABLE 2 TABLE 2 (Continued) TABLE 2 (Continued) Although a preferred system and method incorporating the present invention has been disclosed for illustrative purposes, those skilled in the art will appreciate that many additions, modifications, and substitutions are possible without departing from the scope of the present invention. For example, a system for providing test access to T3 communication links has been described. It is contemplated that the present invention can be used for signals of a substantially higher frequency, such as DS5 signals which, in Europe, provide a capacity of 565,148 Mbps. All of these variations are intended to be within the scope of the invention, as provided in the appended claims.

Claims (32)

1. A system for accessing a plurality of communication lines by one or more test devices, each coupling the plurality of communication lines through the system, and having a first termination at a first telecommunications termination site, and a second termination in a second telecommunications termination site, the system comprising: a plurality of line access devices, each of the line access devices being coupled with at least one of the communication lines terminating in the first site of telecommunications termination, and terminating at least one of the communication lines in the second telecommunications termination site; a plurality of high frequency relays defining a busbar, one or more of the relays being coupled to one of the line access devices; and a test device interface coupled to the busbar, by coupling one or more of the activated relays to a selected communication line with one of the selected test devices, by means of the test device interface, wherein one or more signal paths defined by passing through the line access devices, relays, and test device interface, define trajectories of high frequency signals.

The system of claim 1, wherein one or more signal paths defined by passing through the relays, the test device interface, and a portion of the line access devices, define point-to-point connections. without derivations.

The system of claim 1, wherein the relays, the test device interface, and a portion of the line access devices exhibit characteristics of an unbalanced transmission line having a characteristic impedance approximately equivalent to an impedance of the selected communication line.

The system of claim 1, wherein the communication lines comprise high-speed digital transmission lines characterized by transmission rates of the order of tens or hundreds of megabits per second (Mbps).

The system of claim 1, which further comprises a chassis, wherein each of the line access devices and the test device interface, can be removably inserted into one of a plurality of slots provided in the chassis.

6. The system of claim 5, which further comprises a control device and a communication device, wherein each of the control device and the communication device can be inserted in a removable manner in one of the plurality of slots provided in the chassis.

The system of claim 5, wherein the chassis can be removably mounted to a grille of the equipment.

The system of claim 1, wherein the interface of the test device comprises a test card, the test card comprising one or more visual indicators for communicating an operating state of the test device interface.

The system of claim 1, wherein the interface of the test device comprises a front test card and a subsequent test card, the front test card comprising one or more visual indicators to communicate an operating status of the interface of the test device. test device.

The system of claim 1, wherein each of the line access devices comprises a line card, each of the line cards comprising one or more visual indicators for communicating the operational status information.

11. The system of claim 1, wherein each of the line access devices comprises a backline card coupled with at least one of the communication lines and a front line card, providing the front line control cards to the corresponding subsequent line cards, and comprising one or more visual indicators to communicate the operational status information.

The system of claim 1, wherein each of the line access devices comprises a plurality of input / output connectors.

The system of claim 1, wherein the system is operative in a plurality of operating modes.

The system of claim 1, wherein the system is operational in an environment of cross-connections of digital signals (DSX).

The system of claim 1, which further comprises a communications device, the communication device providing remote access to the system by means of a remote control device.

The system of claim 15, wherein the communication device provides communication of configuration or status information between the system and the remote control device.

17. A system for providing access to a plurality of communication lines by one or more test devices, which comprises: a plurality of line access devices, each of the line access devices being coupled with at least one of the lines of communication; a test device interface; a mother board; and a plurality of high frequency relays defining a busbar, and provided on the motherboard, by coupling one or more of the activated relays to a selected communication line with a selected test device by means of the test device interface , displaying the relays, the test device interface, and a portion of the line access devices characteristic of an unbalanced transmission line having a characteristic impedance approximately equivalent to an impedance of the selected communication line.

The system of claim 17, wherein one or more signal paths defined by passing through the relays, the test device interface, and the portion of the line access devices, define point-to-point connections. without derivations.

The system of claim 17, wherein one or more signal paths defined by passing through the relays, the test device interface, and a portion of the line access devices, are provided on or within a printed circuit board (PCB).

The system of claim 17, wherein the printed circuit board (PCB) comprises multiple layers within which one or more of the signal paths having an in-line configuration of fra j a are provided.

The system of claim 17, wherein one or more signal paths defined by passing through the relays, the test device interface, and the portion of the line access devices, comprise a signal conductor arranged between a plurality of reference planes.

The system of claim 21, further comprising first and second guard conductors respectively disposed on opposite sides of each of the signal conductors, the guard conductors being coupled with the reference planes at predetermined locations, and providing electromagnetic induction protection (EMI).

The system of claim 17, wherein the relays define a plurality of busbar lines, wherein some of the line access devices are coupled with a first busbar line of the plurality of busbar lines. , and some of the line access devices are coupled with a second bus line of the plurality of bus lines.

The system of claim 17, which further comprises a multi-conductor connector that provides coupling between the motherboard and each of the line access devices, providing the configuration of peaks of each of the multi-conductor connectors. an effective impedance representative of a coaxial transmission line.

25. The system of claim 24, wherein the peaks of the connector are configured to include a signal conducting peak around which a plurality of protective conductor peaks are located.

26. The system of claim 17, wherein the communication lines comprise high-speed digital transmission lines, characterized by transmission rates of the order of tens or hundreds of megabits per second (Mbps).

27. A method for providing access to a plurality of high frequency communication lines by one or more test devices, which comprises: selecting one of the plurality of communication lines; selecting one of the plurality of interface outputs of the test device; establishing, using one or more of a plurality of high frequency relays defining a busbar, a high frequency signal conductivity path between the selected communication line and the interface output of the selected test device, exhibiting the path of Signal conductivity characteristics of an unbalanced transmission line having a characteristic impedance approximately equivalent to an impedance of the selected communication line; and providing an information signal transmitted through the selected communication line to the interface output of the selected test device, for access by a test device coupled with the interface output of the selected test device.

The method of claim 27, wherein setting the signal conductivity path further comprises activating one or more relays that selectively couple and uncouple one of the plurality of communication lines with the interface output of the selected test device. .

The method of claim 27, wherein the provision of the information signal further comprises selectively providing the information signal to the interface output of the selected test device, or retro-cycling the information signal to the line of selected communication.

30. The method of claim 27, which further comprises visually indicating a state of the selected communication line or a test device coupled with the interface output of the selected test device.

The method of claim 27, wherein selecting one of the plurality of communication lines further comprises remotely selecting one of the plurality of communication lines.

32. The method of claim 27, wherein selecting one of the plurality of interface outputs of the test device further comprises remotely selecting one of the plurality of interface outputs of the test device.