MX345595B - Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 64-symbol mapping, and bit interleaving method using same.
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Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 64-symbol mapping, and bit interleaving method using same.
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Priority claimed from KR1020150009441Aexternal-prioritypatent/KR102260752B1/en
Application filed by Electronics & Telecommunications Res InstfiledCriticalElectronics & Telecommunications Res Inst
Publication of MX2015002226ApublicationCriticalpatent/MX2015002226A/en
Publication of MX345595BpublicationCriticalpatent/MX345595B/en
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
MX2015002226A2014-02-202015-02-19Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 5/15 and 64-symbol mapping, and bit interleaving method using same.
MX345595B
(en)
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