LU503256A1 - 2.5d chiplet arrangement method for optimizing communication power consumption - Google Patents

2.5d chiplet arrangement method for optimizing communication power consumption Download PDF

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LU503256A1
LU503256A1 LU503256A LU503256A LU503256A1 LU 503256 A1 LU503256 A1 LU 503256A1 LU 503256 A LU503256 A LU 503256A LU 503256 A LU503256 A LU 503256A LU 503256 A1 LU503256 A1 LU 503256A1
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mapped
chiplet
power consumption
unit cell
communication power
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LU503256A
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German (de)
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LU503256B1 (en
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Xinwei Peng
Yanhua Liu
Jiaen Fang
Haiyan Sun
Jicong Zhao
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Suzhou Rigger Micro Tech Group Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
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  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

The present invention discloses a 2.5D chiplet arrangement method for optimizing communication power consumption, comprising: determining a theoretical value of a dimension of each chiplet based on a proportional relationship and an arrangement spacing between respective chiplets; determining a size of a topology based on theoretical values of dimensions of all chiplets, and dividing the topology into a number of first unit cells of equal dimension; successively confirming, in descending order according to amount of communication data of a chiplet to be mapped and arranged, a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed, so as to form mapping and arranging modes; calculating overall communication power consumption of each mapping and arranging mode; and selecting a mapping and arranging mode corresponding to an overall communication power consumption of a minimum value as a final mapping and arranging mode. The present application can achieve least communication power consumption among chiplets on a silicon carrier board in 2.5D integration and reduce an area of the topology, effectively solving the problems of power consumption and heat dissipation in 2.5D integration and reducing the cost.

Description

2.5D CHIPLET ARRANGEMENT METHOD FOR OPTIMIZING
COMMUNICATION POWER CONSUMPTION
TECHNICAL FIELD
The present invention relates to the field of semiconductor technology, and in particular to a 2.5D chiplet arrangement method for optimizing communication power consumption.
BACKGROUND
With the continuous progress of technology, integrated circuits (ICs) are developing towards high performance, high integration, low cost and low power consumption. The emergence of deep submicron process technology enables the integration of circuit systems with complete functionality onto a single chip, enabling an IP core multiplexing-based system-on-chip (SoC).
However, as the IC feature dimension continues to decrease, the increasing number of IP cores on a single chip requires longer and more complex wiring, highlighting the problem of interconnect line delays. In addition, as semiconductor processes continue to advance, the cost of chip design increases exponentially and development cycles are long. Therefore, 2.5D
ICs based on silicon adapter boards have been widely focused. Since 2.5D integration uses chiplet technology, the area of a single chiplet is much smaller than that of a SoC, so the yield of a chiplet is much higher than that of a SoC chip and the cost is much lower than that of a SoC chip. 2.5D ICs have more powerful system performance and lower power consumption, and support heterogeneous integration. Packaging the internal chiplet does not require the use of the same semiconductor process node, greatly reducing the cost of chip design. It has shown amazing development potential in solving the problems of power consumption, delay, operating frequency, integration, heterogeneous integration, and cost of the
ICs. However, the whole process of 2.5D integration design inevitably involves chiplet layout or arrangement on a silicon adapter board. The chiplet arrangement has a large impact on the heat dissipation of the 2.5D integration and the communication power consumption among the chiplets.
Therefore, a chiplet arrangement algorithm is proposed.
SUMMARY OF THE INVENTION
In view of the shortcomings of the prior art, the present invention provides a 2.5D chiplet arrangement method for optimizing communication power consumption, in which theoretical values of dimensions of chiplets and a size of an overall topology in the arrangement design are reasonably designed, and all chiplets are reasonably mapped and arranged in the topology, so that the communication power consumption among chiplets on the silicon carrier board in 2.5D integration is minimized, effectively solving the problems of power consumption and heat dissipation in 2.5D integration and reducing the cost.
According to an aspect of the present application, a 2.5D chiplet arrangement method for optimizing communication power consumption is provided, which comprises: determining a theoretical value of a dimension of each chiplet based on a proportional relationship and an arrangement spacing between respective chiplets; determining a size of a topology based on theoretical values of dimensions of all chiplets, and dividing the topology into a number of first unit cells of equal dimension, a length of the first unit cell being a common divisor of lengths of the theoretical values of the dimensions of all the chiplets, and a width of the first unit cell being a common divisor of widths of the theoretical values of the dimensions of all the chiplets; successively confirming, in descending order according to amount of communication data of a chiplet to be mapped and arranged, a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed so as to form mapping and arranging modes; calculating overall communication power consumption of each mapping and arranging mode; and selecting a mapping and arranging mode corresponding to a minimum value of an overall communication power consumption as a final mapping and arranging mode.
According to the 2.5D chiplet arrangement method for optimizing communication power consumption of the present application, by determining the theoretical value of the dimension of each chiplet and dividing the topology, it is possible to determine the size of the interval between the chiplet arrangement positions when arranging the chiplets, avoiding the arrangement interval from being too large or too small due to the different sizes and positions of the chiplets. In addition, the chiplets are arranged closely and the area of the overall topology is reduced so that the overall heat dissipation effect can be improved. At the same time, by calculating the overall communication power consumption of various mapping and arranging modes, it is possible to ensure a compact chiplet arrangement while minimizing the communication power consumption among chiplets in the topology, effectively solving the problems of 2.5D integration in terms of power consumption and heat dissipation, and reducing the cost.
In some embodiments, after confirming a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed, the first unit cell corresponding to the mapped and arranged position is marked to indicate that the first unit cell has been mapped and arranged with the chiplet.
Thus, the first unit cell corresponding to the chiplet for which the mapped and arranged position has been determined on the topology can be recorded by marking, so that the mapped and arranged positions can be better determined for the remaining chiplets to be mapped and arranged afterwards.
In some embodiments, when confirming a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed, a mapped and arranged position at which a least increase in communication power consumption occurs after being so mapped and arranged is selected as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation based on a communication relationship between the chiplet with a confirmed mapped and arranged position and a chiplet to be mapped and arranged.
As a result, with the communication relationship between the chiplet for which the mapped and arranged position has been confirmed and the chiplet to be mapped and arranged, and through the calculation of an increased communication power consumption of the chiplet to be mapped and arranged after being so mapped and arranged at the selected mapped and arranged position, a minimum value can be selected to further reduce the computation burden for subsequent mapped and arranged positions.
In some embodiments, to select a mapped and arranged position at which a least increase in communication power consumption occurs after being so mapped and arranged as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation based on a communication relationship between the chiplet with a confirmed mapped and arranged position and a chiplet to be mapped and arranged, the following steps may be implemented determining all mappable and arrangeable positions of the chiplet to be mapped and arranged; calculating an increased communication power consumption of the chiplet to be mapped and arranged after being mapped and arranged at each mappable and arrangeable position; and selecting a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
Thus, it is possible to determine the mapped and arranged position with least communication power consumption in order to reduce the computation burden for subsequent mapped and arranged positions, by selecting all mappable and arrangeable positions of the chiplets to be mapped and arranged on the current topology, and calculating the increased communication power consumption of the chiplets to be mapped and arranged after being arranged at each mappable and arrangeable position.
In some embodiments, to determine all mappable and arrangeable positions of the chiplet to be mapped and arranged, the following step may be implemented: dividing the chiplet to be mapped and arranged into a number of second unit cells each having a same dimension as the first unit cell; selecting a second unit cell in an upper left corner of the chiplet as a marking point, wherein the marking point of the chiplet being set on a first unit cell indicates that the first unit cell is the mapped and arranged position of the chiplet on the topology; performing a comparison and calculation on the first unit cell where a chiplet has not been confirmed to be mapped and arranged in order to select all first unit cells satisfying a first condition as all the mappable and arrangeable positions, where the first condition is: each of ranges enclosed by a length of a right side L and a length of a lower side W of the first unit cell is located within the topology, and in each of the ranges enclosed by a length of a right side L and a length of a lower side W of the first unit cell, no mapped and arranged chiplet has been confirmed, where L is a length of the chiplet, and W is a width of the chiplet.
As a result, it is possible to quickly select all satisfactory first unit cells by marking the chiplet to be mapped and arranged, and thus quickly and accurately find all the mappable and arrangeable positions.
In some embodiments, the method further comprises that, when selecting a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation, the following steps are implemented when there are at least two mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value:
calculating a minimum value of an increased communication power consumption of next chiplet to be mapped and arranged after being mapped and arranged when the current chiplet to be mapped and arranged is mapped and arranged at each of the mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value; selecting a mappable and arrangeable position corresponding to the increased communication power consumption of the minimum value of the chiplet to be mapped and arranged after being mapped and arranged, for which the increased communication power consumption of the next chiplet to be mapped and arranged after being mapped and arranged has a smaller minimum value, as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
Thus, by calculating the increased communication power consumption of next chiplet to be mapped and arranged after being mapped and arranged, it is possible to determine the selection of the mapped and arranged position when there are more than two mapped and arranged positions with the same minimum value of increased communication power consumption, so that a best position can be directly selected each time the mapped and arranged position of the chiplet to be mapped and arranged is selected, in order to effectively reduce the computation burden for the subsequent mapped and arranged positions of chiplets to be mapped and arranged and improve the overall computation speed and efficiency.
In some embodiments, wherein a side length of the first unit cell is a common divisor of lengths and widths of the theoretical values of the dimensions of all the chiplets, and the determining all mappable and arrangeable positions of the chiplet to be mapped and arranged comprises determining respectively all mappable and arrangeable positions of the chiplet to be mapped and arranged when being placed laterally and all mappable and arrangeable positions of the chiplet to be mapped and arranged when being placed longitudinally.
As a result, the mapping and arranging mode with the minimum overall communication power consumption can be better determined by separately identifying the mappable and arrangeable positions satisfying lateral and longitudinal placement specifications respectively, in order to address the problems of 2.5D integration in terms of power consumption and heat dissipation.
In some embodiments, a side length of the first unit cell is the greatest common divisor of lengths and widths of the theoretical values of the dimensions of all the chiplets.
By setting the dimension of the first unit cell in this way, the number of first unit cells used to represent the mapped and arranged position of the chiplet is effectively reduced, reducing the computation burden as well as increasing the overall computation speed and improving the efficiency.
According to another aspect of the present invention, an electronic device is provided, including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform steps of the above-mentioned method.
According to a further aspect of the present invention, a storage medium is provided, which stores a computer program, wherein the program implements steps of the above-mentioned method when executed by a processor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a flowchart of steps of a 2.5D chiplet arrangement method for optimizing communication power consumption of an embodiment of the present invention;
FIG. 2 is a flowchart of step S103 in FIG. 1;
FIG. 3 is a flowchart of step S201 in FIG. 2;
FIG. 4 is a flowchart of the selection of the mappable and arrangeable position when there are more than one mappable and arrangeable positions corresponding to the minimum value of increased communication power consumption in step S303 in FIG. 2;
FIG. 5 is a comparison of Manhattan distance for lateral placement and longitudinal placement of chiplets;
FIG. 6 is a diagram of an initial mapping and arranging mode for a 2.5D integration with 22 chiplets;
FIG. 7 is a diagram of the core communication task for the chiplets in
FIG. 6;
FIG. 8 is an order table in descending order of the amount of communication data for the chiplets in FIG. 6;
FIG. 9 is a diagram of the mappable and arrangeable positions of the chiplet in FIG. 6 with the largest amount of communication data;
FIG. 10 is a diagram of the resulted mapping and arranging mode of the all in 2.5D integration of FIG. 6;
FIG. 11 is a diagram of the final mapping and arranging mode for the 2.5D integration of FIG. 6.
DETAILED DESCRIPTION
The present invention will be described in further detail below in conjunction with the drawings.
FIGs. 1 to 5 schematically show a flowchart of a 2.5D chiplet arrangement method for optimizing communication power consumption of the present application.
Referring to FIG. 1, according to an aspect of the present application, a 2.5D chiplet arrangement method for optimizing communication power consumption is provided, which comprises:
Step S101, determining a theoretical value of a dimension of each chiplet based on a proportional relationship and an arrangement spacing between respective chiplets.
The proportional relationship between respective chiplets should be interpreted as a proportional relationship between respective chiplets formed by the difference in dimension between respective different chiplets.
At the same time, because it is also necessary to take the arrangement spacing between respective chiplets into consideration when the chiplet is mapped and arranged on the topology, the theoretical value of dimension of each chiplet is set according to the proportional relationship and the arrangement spacing between respective chiplets, so that all the chiplets can form a unified specification, avoiding that the various chiplet dimensions with different proportions lead to interlacing in mapping and arranging the chiplets.
Step S101 can be implemented as follows. According to the proportional relationship between the lengths and that between the widths of respective chiplets to be mapped and arranged on the topology, a minimum spacing of the chiplets required after being mapped and arranged is taken into consideration, and the arrangement spacings are rounded up,
in order to derive the theoretical value of the dimension of each chiplet with a multiple relationship between the length values and between the width values. This allows that the chiplets can be well spaced upon being mapped and arranged according to the theoretical values of the dimensions and do not suffer from being interlaced.
Step S102, determining a size of a topology based on theoretical values of dimensions of all chiplets, and dividing the topology into a number of first unit cells of equal dimension. A length of the first unit cell is a common divisor of lengths of the theoretical values of the dimensions of all the chiplets, and a width of the first unit cell is a common divisor of widths of the theoretical values of the dimensions of all the chiplets.
In step S102, it is necessary to derive a total area occupied by all chiplets according to the theoretical values of dimensions of all chiplets, in order to determine the size of the topology on which the chiplets are to be mapped and arranged.
In step S102, in order to divide the topology into the first unit cells related to the theoretical value of dimension of each chiplet determined in step S101, in the division, since there is a multiple relationship between the theoretical values of dimension of respective chiplets determined in step
S101, the length dimension of a first unit cell is designed as a common divisor corresponding to lengths of the theoretical values of dimension of respective chiplets, and the width dimension of the first unit cell is designed as a common divisor corresponding to widths of the theoretical values of dimension of each chiplet, so that when the chiplets are mapped and arranged on the topology, it is possible to determine which first unit cells on the topology is to be arranged with the chiplets according to the theoretical values of dimensions of the chiplets. In this way, the mapped and arranged positions of the chiplets can be scheduled to allow the chiplets to have good arrangement spacing with each other upon being mapped and arranged and avoide to be interlaced.
In some embodiments, the first unit cell can be set as a square for the selection of the length dimension and the width dimension of the first unit cell. The side length of the first unit cell is set to be the maximum common divisor of the lengths and widths of the theoretical values of the dimensions of all chiplets, so that when performing the mapping and arrangement, the effect of the lateral and longitudinal placement of the chiplets on the results can be taken into account. In addition, the number of the first unit cells for use can be effectively reduced when a mapped and arranged position of a chiplet on the topology is represented by the first unit cell, so as to reduce the overall computation burden of the arrangement method, effectively improve the overall computation speed, and improve the arrangement efficiency.
Step S103, successively confirming in an descending order, according to amount of communication data of a chiplet to be mapped and arranged, a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell of the topology where a mapped and arranged position of a chiplet has not been confirmed so as to form mapping and arranging modes.
In step S103, the confirming a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell of the topology where a mapped and arranged position of a chiplet has not been confirmed should be interpreted as finding a first unit cell on the topology corresponding to a position where the chiplet to be mapped and arranged is to be mapped and arranged, but not a real mapping and arranging of the chiplet to the corresponding mapped and arranged position. In an implementation, the corresponding chiplet can be optionally mapped and arranged at the corresponding mapped and arranged position according to the actual situation. It is also possible to mark only the mapped and arranged position to indicate that a chiplet is confirmed to be mapped and arranged on the first unit cell corresponding to the mapped and arranged position, avoiding arrangement errors when mapping and arranging the remaining chiplets to be mapped and arranged. The mark can be a serial number or a mark number of a chiplet that has been confirmed to be mapped and arranged on the first unit cell. At the same time, a first unit cell where a chiplet has not been confirmed to be mapped and arranged can also be marked to indicate that the first unit cell is in a state that no chiplet has been mapped and arranged.
In step S103, before mapping and arranging a chiplet to be mapped and arranged, all the chiplets are ranked. The ranking is based on the amount of communication data. The larger the amount of communication data, the higher the priority for mapping and arranging the chiplet is. In this way, it allows the mapped and arranged position of the chiplet with a largest amount of communication data to be selected first, so that when mapping and arranging a chiplet with a next highest ranking, an excessive increased communication power consumption after the mapping and arrangement of the chiplet, which is resulted from the limitation of remaining mappable and arrangeable positions that are available, can be avoided. In general, the larger the amount of communication data of a chiplet, the larger the area to be occupied by the chiplet in the mapping and arrangement, and thus it also helps to improve the utilization of the topology area in the mapping and arrangement.
Specifically, in the formation of a mapping and arranging mode, a chiplet with the largest communication power consumption is used as a first chiplet to be mapped and arranged on the topology. In the mapping and arrangement, all the first unit cells on the topology are in the state where a chiplet has not been confirmed to be mapped and arranged. Thus, any position on the topology can be used as the mapped and arranged position of the chiplet with the highest communication power consumption for confirmation. When confirming the mapped and arranged position of a next chiplet, since the mapped and arranged position of the previous chiplet is already confirmed on the current topology, it is necessary to select a mappable and arrangeable position, which is an alternative position, on the remaining first unit cells as the mapped and arranged position of the chiplet for confirmation.
When confirming the mapped and arranged position of the next chiplet, a mapped and arranged position can also be selected based on a communication relationship between the chiplet with a confirmed mapped and arranged position on the topology and the chiplet to be mapped and arranged, and a mapped and arranged position of the chiplet to be mapped and arranged is selected as a mapped and arranged position with a least increase in communication power consumption of the chiplet to be mapped and arranged upon being mapped and arranged for confirmation. In this way, it can directly exclude a mapping and arranging mode with a higher communication power consumption each time the mapped and arranged position of the chiplet is confirmed, increasing the number of mapping and arranging modes finally obtained from calculation, reducing the computation amount, and improving the computation speed and arrangement efficiency.
Referring to FIG. 2, the process of step S103 includes the following steps.
Step S201, determining all mappable and arrangeable positions of the chiplet to be mapped and arranged.
In step S201, the mappable and arrangeable positions should be interpreted as positions on the topology where the chiplet to be mapped and arranged can be mapped and arranged. Since there may be a chiplet with a confirmed mapped and arranged position before confirming the mapped and arranged position of the chiplet to be mapped and arranged, there may be a first unit cell on the topology corresponding to the chiplet with a confirmed mapped and arranged position. In combination with the boundary of the topology and the theoretical value of dimension of the chiplet to be mapped and arranged, all the mappable and arrangeable positions of the chiplet to be mapped and arranged on the topology are confirmed.
In some embodiments, since the structures of the chiplets are not all equilateral, it is also necessary to consider the effect of the lateral and longitudinal placement of a chiplet on the increase of communication power consumption. The increased communication power consumption can be calculated according to the following equation.
E = d Lk,
Where d; ; is the Manhattan distance between center points of chiplet i and chiplet j, and Ep; is the power consumption required to transmit 1 bit of data between chiplets per unit distance. In calculating the Manhattan distance, reference is made to the center point of chiplet. Referring to FIG. 5, the Manhattan distance between chiplet_0 and chiplet_2 is 2.5 units when chiplet 2 is placed laterally, and 3.5 units when chiplet 2 is placed longitudinally. Thus, it is necessary to take the states of lateral placement and longitudinal placement of the chiplet into consideration when determining all mappable and arrangeable positions.
Referring to FIG. 3, step S201 can include the steps as follows.
Step S301, dividing the chiplet to be mapped and arranged into a number of second unit cells each having a same dimension as the first unit cell.
In step S301, since the dimension of the first unit cell is associated with the theoretical value of the dimension of the chiplet, the chiplet can be easily divided into a number of second unit cells so that the position of the second unit cell corresponds to the position of the first unit cell when the chiplet is mapped and arranged on the topology.
Step S302, selecting a second unit cell in an upper left corner of the chiplet as a marking point. The marking point of the chiplet being set on a first unit cell indicates that the first unit cell is the mapped and arranged position of the chiplet on the topology.
In step S302, the mapped and arranged position of the chiplet on the topology is reduced from a plurality of second unit cells to the second unit cell where the marking point is located. The second unit cell where the marking point is located represents the chiplet to be arranged, and the first unit cell where the marking point is set on the topology represents the mapped and arranged position of the chiplet on the topology.
Step S303, performing a comparison and calculation on the first unit cell where a chiplet has not been confirmed to be mapped and arranged in order to select all first unit cells satisfying a first condition as all the mappable and arrangeable positions. The first condition is: each of ranges enclosed by a length L of a right side and a length W of a lower side of the first unit cell is located within the topology, and no mapping and arrangement of chiplet has been confirmed in each of the ranges enclosed by a length L of a right side and a length W of a lower side of the first unit cell, where L is a length of the chiplet, and W is a width of the chiplet.
The comparison and calculation described in step S303 should be interpreted as a calculation of whether the first unit cell satisfies the first condition. Since a general topology is a regular square structure, the comparison and calculation is to compare and calculate whether a distance from the first unit cell to each boundary of the topology (upper, lower, left, and right boundaries) is not less than a distance from the marking point to each corresponding boundary of the chiplet, indicating whether the marking point of the chiplet will go beyond the boundary of the topology when it is set on the first unit cell, and when the chiplet is mapped and arranged on the first unit cell, whether there is a conflict with the first unit cell on the topology where a chiplet is already mapped and arranged.
Since in the present embodiment, the marking point is set to the second unit cell in the upper left corner of the chiplet, the first condition should be interpreted in this embodiment as follows: when the chiplet is set on the first unit cell, the distance from the first unit cell to the lower boundary of the topology should be no less than the distance from the marking point to the lower boundary of the chiplet, and the distance from the first unit cell to the right boundary of the topology should be no less than the distance from the marking point to the right boundary of the chiplet, and no mapping and arrangement of chiplet is confirmed within a range surrounded by the length L of the right side and the length W of the lower side of the first unit cell. Here, L is a length of the chiplet, and W is a width of the chiplet.
Through the above steps S301 to S303, all the mappable and arrangeable positions of the chiplet to be mapped and arranged can be effectively selected, and the computation burden can be reduced to improve the overall computation speed and arrangement efficiency.
Turning to FIG. 2, in step S202, calculation is performed on an increased communication power consumption of the chiplet to be mapped and arranged upon being mapped and arranged at each mappable and arrangeable position.
In step S202, a comparison and calculation is performed on all of the mappable and arrangeable positions determined in step S201 to derive the increased communication power consumption of the chiplet to be mapped and arranged at each of the mappable and arrangeable positions, in order to determine the impact of the chiplet to be mapped and arranged after being mapped and arranged at each of the mappable and arrangeable positions on the overall communication power consumption.
In step S203, a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value is selected as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
In step S203, based on the increased communication power consumption of the chiplet to be mapped and arranged after being mapped and arranged at each of the mappable and arrangeable positions calculated in step S202, a mappable and arrangeable position with the least increased communication power consumption is selected as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation. In this way, it can directly exclude a mapping and arranging mode with a higher communication power consumption when the mapped and arranged position of the chiplet is confirmed, increasing the number of mapping and arranging modes finally obtained from calculation, reducing the computation burden, and improving the computation speed and arrangement efficiency.
In step S203, when selecting a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation, there may be more than one (i.e., at least two) mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value. In this case, the following steps can be used to determine the mappable and arrangeable position that should be selected. Referring to FIG. 4, the following steps are included.
Step S401, calculating a minimum vale of an increased communication power consumption of next chiplet to be mapped and arranged after being mapped and arranged when the chiplet to be mapped and arranged is mapped and arranged at each of the mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value.
In step S401, all the mappable and arrangeable positions with the increased communication power consumption of the same minimum value are selected first. Based on the condition that the chiplet to be mapped and arranged is mapped and arranged on the mappable and arrangeable positions, a minimum value of the increased communication power consumption of a next chiplet to be mapped and arranged after being mapped and arranged is calculated, and the minimum value of the increased communication power consumption of the next chiplet to be mapped and arranged after being mapped and arranged is used as selection criteria of the mappable and arrangeable position of the chiplet to be mapped and arranged.
Step S402, selecting a mappable and arrangeable position corresponding to the increased communication power consumption of the minimum value of the chiplet to be mapped and arranged after being mapped and arranged, for which the increased communication power consumption of the next chiplet to be mapped and arranged after being mapped and arranged has a smaller minimum value, as a mapped and arranged position of the chiplet to be mapped and arranged.
In step S402, based on the minimum value of the increased communication power consumption of the next chiplet to be mapped and arranged after being mapped and arranged calculated in step S401, a mappable and arrangeable position of the chiplet to be mapped and arranged corresponding to a smaller value is selected as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
Through steps S401 to S402, by calculating the increased communication power consumption of next chiplet to be mapped and arranged after being mapped and arranged, it is possible to determine the selection of the mapped and arranged position when there are more than two mapped and arranged positions with the same minimum value of increased communication power consumption, so that a best position can be directly selected each time the mapped and arranged position of the chiplet to be mapped and arranged is selected, in order to effectively reduce the computation burden for the subsequent mapped and arranged positions of chiplets to be mapped and arranged and improve the overall computation speed and efficiency.
So far, in step S103, the above steps are repeated to confirm the mapped and arranged position of each chiplet to be mapped and arranged, finally forming a mapping and arranging mode. Among them, since in confirming the mapped and arranged position of the chiplet with the largest communication power consumption, there are no other chiplets for which the mapped and arranged positions have been determined, a mapping and arranging mode corresponding to all the mapped and arranged positions confirmed for the chiplet with the largest communication power consumption can be listed as an alternative mapping and arranging mode.
Turning to FIG. 1, in step S104, calculation of overall communication power consumption of each mapping and arranging mode is performed.
In step S104, since all the mapping and arranging modes derived from step S103 are calculated by successively mapping and arranging in descending order based on the amount of communication data of the chiplet to be mapped and arranged, the areas of all the mapping and arranging modes derived from step S103 are the same and the smallest. Therefore, in step S104, only the overall communication power consumption of all mapping and arranging modes derived from step S103 can be calculated as a determination condition for the advantages and disadvantages of the mapping and arranging modes.
In step S105, a mapping and arranging mode corresponding to an overall communication power consumption of a minimum value is selected as a final mapping and arranging mode.
In step S105, for the overall communication power consumption for each mapping and arranging mode calculated in step S104, a mapping and arranging mode with the least overall communication power consumption is selected as the finally determined mapping and arranging mode. According to this mapping and arranging mode, the arrangement position in mapping and arranging can be derived for the topology and chiplet, which can effectively improve the overall heat dissipation effect and reduce the communication power consumption.
According to the 2.5D chiplet arrangement method for optimizing communication power consumption of the present application, by determining the theoretical value of the dimension of each chiplet and dividing the topology, it is possible to determine the size of the interval between the chiplet arrangement positions when arranging the chiplets, avoiding the arrangement interval being too large or too small due to the different sizes and positions of the chiplets. In addition, the chiplets are arranged closely and the area of the overall topology is reduced so that the overall heat dissipation effect can be improved. At the same time, by calculating the overall communication power consumption of various mapping and arranging modes, it is possible to ensure a compact chiplet arrangement while minimizing the communication power consumption among chiplets in the topology, effectively solving the problems of 2.5D integration in terms of power consumption and heat dissipation and reducing the cost.
A 2.5D integration with 22 chiplets is provided as an example. FIG. 6 is a diagram of an initial mapping and arranging mode of the 2.5D integration, of which the overall communication power consumption is 1209.56 uJ, FIG. 7 shows the core communication task diagram of the corresponding chiplets, and FIG. 8 is an order table of the chiplets used in FIG. 5. In FIG. 8, the amount of communication data of the chiplets for mapping and arrangement is listed in descending order, and corresponding serial number names and actual dimension values of the chiplets are also shown in FIG. 8.
According to step S101, a theoretical value of a dimension of each chiplet is determined based on a proportional relationship and an arrangement spacing between respective chiplets. The specific theoretical values of dimensions as determined are shown in FIG. 8, where 3mm is the smallest theoretical value of dimension. Each of the theoretical values of dimensions of the other chiplets is several times of the smallest theoretical value of dimension.
According to step S102, the size of the area occupied by all chiplets is calculated to determine the size of the topology, and the topology is divided.
The length and width of the first unit cell as divided are both common divisors of the theoretical values of dimensions of the chiplets, such as 3 mm or 1 mm. The maximum common divisor is selected as the length and width of the first unit cell, and the topology is divided into a number of first unit cells of 3 mm x 3 mm. In particular, referring to FIG. 9, the topology is square and is divided into 8 x 7 first unit cells.
When successively confirming the mapped and arranged position of each chiplet on the topology in descending order based on the amount of the communication data according to step S103, the position of the marking point for indicating the chiplet can be determined first. Since the dimension of the chiplet has a proportional relationship with the dimension of the first unit cell, the chiplet can be easily divided into several second unit cells. A second unit cell located in the upper left corner of the chiplet is selected as the marking point to reduce the computation for confirming the mappable and arrangeable position.
The mapped and arranged position of the chiplet with the largest amount of communication data on the topology is first confirmed according to step S201, and that is, the mapped and arranged position of chiplet 4 on the topology is confirmed. Since a mapped and arranged position of other chiplet has not been confirmed on the current topology, chiplet_4 can be mapped and arranged at any position on the topology. According to step
S301, chiplet_ 4 is divided into a number of second unit cells, and the specific dimension of chiplet_4 is 4 x 4 second unit cells, and according to step S302, a second unit cell in the upper left corner of chiplet 4 is set as a marking point. Referring to FIG. 9, since certain mapped and arranged positions are symmetrical with each other (suchasavsd,bvsc,andavsg in FIG. 9) on the topology at the time of arrangement, these mapped and arranged positions with symmetrical relationships should have the same power consumption, and therefore the mapped and arranged positions with symmetrical relationships can be considered as the same mapped and arranged position at the time of design. Specifically, the number of mappable and arrangeable positions of chiplet_ 4 on the topology can be calculated according to the following equation. x= ceil 3 y= cl?
M=x-y
Where ceil is a rounding up function, N; is the length of the topology, Nz is the width of the topology, Lo is the length of the chiplet with the largest amount of communication data, Wo is the width of the chiplet with the largest amount of communication data, and M is the number of mappable and arrangeable positions. According to the theoretical value of the dimension of chiplet_4, the number of mappable and arrangeable positions is 6. In this case, when the chiplet is mapped in (h) of FIG. 9, next chiplet 0 (with a dimension of 3 x 3 second unit cells) to be mapped cannot be mapped in the remaining topology, and thus a result will not be obtained in this case.
This case will be excluded, and thus the number of mapped and arranged positions for consideration is 5.
The mappable and arrangeable position is obtained by performing a comparison and calculation on the first unit cells according to step S303.
Since the marking point is the second unit cell in the upper left corner of the chiplet, a comparison and calculation of the distance in the left and upper directions of the chiplet can be omitted in the comparison and calculation.
Also, since chiplet_4 is the first chiplet for which the mapped and arranged position is determined, there is no need to perform a comparison and calculation with the distance to the mapped and arranged position already determined on the topology. Therefore, referring to FIG. 9, the mapped and arranged position corresponding to the first unit cell be used as the mapped and arranged position of chiplet_4 provided that the distance from the first unit cell to the right boundary of the topology is not less than the length of chiplet_4, and the distance from the first unit cell to the lower boundary of the topology is not less than the width of chiplet_4an.
When the mapped and arranged position of the first chiplet is confirmed, the first unit cell on the topology can be marked to indicate the first unit cell with the confirmed mapped and arranged position on the topology. Referring to FIG. 9, specifically, this marking may be to mark the confirmed mapped and arranged position of chiplet 4 as 4, while the remaining first unit cells where a chiplet has not been confirmed to be mapped and arranged may be marked in other ways. In this example, since there are chiplets with serial numbers from O to 21, the first unit cell where a chiplet has not been mapped and arranged can be marked as -1, and the actual marking can be done with other letters.
Afterwards, a mapped and arranged position of a next chiplet to be mapped and arranged on the topology is confirmed, i.e., confirming a mapped and arranged position of the chiplet (chiplet 0) with the second largest amount of communication data on the topology. Since chiplet_O is of a square structure, there is no need to separately confirm the mappable and arrangeable position of chiplet 0 when laterally placed and the mappable and arrangeable position of chiplet 0 when longitudinally placed. For a dimension ratio of 2 x 1 second unit cells of chiplet_5, it is necessary to separately confirm the mappable and arrangeable position when laterally placed and the mappable and arrangeable position when longitudinally placed. Since the mapped and arranged position of chiplet 4 has been confirmed on the current topology, chiplet O needs to be mapped and arranged on the remaining first unit cells marked with -1 on the topology.
Chiplet_0 has a dimension of 3 x 3 second unit cells. After confirming the mappable and arrangeable positions of chiplet O according to the first condition in step S303, the increased communication power consumption of chiplet 0 after being mapped and arranged at each mappable and arrangeable position is calculated. The increased communication power consumption can be calculated by the following equation.
Ej = dijEbu
Where d; ; is the Manhattan distance between center points of chiplet i and chiplet j, and Ep; is the power consumption required to transmit 1 bit of data between chiplets per unit distance. In this example, En: is specifically defined to be 186nJ/Mb.
According to the calculation of the increased communication power consumption based on the above equation, a mappable and arrangeable position with a least increased communication power consumption is selected according to step S203 as the mapped and arranged position of chiplet_O for confirmation, i.e., completing the confirmation of the mapped and arranged position of the chiplet on the topology.
If there are two mappable and arrangeable positions for which chiplet 0 has the same and smallest increased communication power consumption after being mapped and arranged, the mapped and arranged position of the next chiplet (i.e., chiplet_1) is confirmed and the corresponding increased communication power consumption AE; and AE; are calculated. 4E; and
AE; are compared, and a mappable and arrangeable position of chiplet_0 corresponding to the smaller is selected as the mapped and arranged position of chiplet_O for confirmation.
After that, it is only necessary to repeat step S103 to successively confirm mapped and arranged positions of the remaining chiplets on the topology in descending order based on amount of communication data, so as to complete the mapping and arranging mode. Since when confirming the mapped and arranged position of chiplet_4, there is not a confirmed mapped and arranged position on the topology, corresponding mapping and arranging modes are derived based on six mapped and arranged positions of chiplet_4. Among them, the mapped and arranged position of chiplet_4 corresponding to (h) in FIG. 9 will prevent chiplet O from being mapped in the remaining first unit cells, and thus this mapping and arranging mode is excluded and the corresponding five mapping and arranging modes are finally derived, as shown in (a) to (f) of FIG. 10. The designed mapping and arranging modes each has only one first unit cell where no chiplet is mapped and arranged. It can be seen that the method can reduce the size of the topology as much as possible, and the length and width of the topology can also be changed according to different requirements to further improve the utilization of the first unit cell of the topology.
By respectively calculating the overall communication power consumption for each of the five mapping and arranging modes, the mapping and arranging mode in (d) of FIG. 10 has the lowest overall communication power consumption of 943.95 nJ, which can be used as the final mapping result of the 2.5D chiplet microsystem design algorithm. The corresponding chiplet is mapped and arranged on the topology as in (d) of
FIG. 10, resulting in a final mapping and arranging mode in FIG. 11. This final mapping and arranging mode reduces the overall power consumption by 22.0% compared to the initial arranging mode corresponding to FIG. 6, effectively reducing the communication power consumption of the chiplet on the topology and solving the problems of 2.5D integration in terms of power consumption and heat dissipation.
In some embodiments, an embodiment of the present invention provides a non-volatile computer-readable storage medium storing one or more programs including execution instructions therein. The execution instructions can be read and executed by an electronic device (including but not limited to a computer, a server, or a network equipment, etc.) to perform the above-mentioned 2.5D chiplet arrangement method for optimizing communication power consumption of the present invention.
In some embodiments, an embodiment of the present invention further provides a computer program product including a computer program stored on a non-volatile computer-readable storage medium, which includes program instructions enabling a computer to perform the above-mentioned
2.5D chiplet arrangement method for optimizing communication power consumption upon being executed by the computer.
In some embodiments, an embodiment of the present invention further provides an electronic device, comprising at least one processor and a memory communicatively connected to the at least one processor. The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the above-described 2.5D chiplet arrangement method for optimizing communication power consumption.
In some embodiments, an embodiment of the present invention further provides a storage medium on which a computer program is stored, and when the program is executed by a processor, the above-mentioned 2.5D chiplet arrangement method for optimizing communication power consumption is performed.
The above embodiments are used only to illustrate the technical solutions of the present application, and not to limit them. A person of ordinary skill in the art should understand that it is still possible to modify the technical solutions disclosed in the embodiments, or to replace some of the technical features with equivalent ones. These modifications or replacements do not make the essence of the corresponding technical solutions out of the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A 2.5D chiplet arrangement method for optimizing communication power consumption, comprising: determining a theoretical value of a dimension of each chiplet based on a proportional relationship and an arrangement spacing between respective chiplets; determining a size of a topology based on theoretical values of dimensions of all chiplets, and dividing the topology into a number of first unit cells of equal dimension, a length of the first unit cell being a common divisor of lengths of the theoretical values of the dimensions of all the chiplets, and a width of the first unit cell being a common divisor of widths of the theoretical values of the dimensions of all the chiplets; successively confirming, in descending order according to amount of communication data of a chiplet to be mapped and arranged, a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed so as to form mapping and arranging modes; calculating overall communication power consumption of each mapping and arranging mode; and selecting a mapping and arranging mode corresponding to a minimum value of an overall communication power consumption as a final mapping and arranging mode.
2. The method according to claim 1, further comprising: after confirming a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed, marking the first unit cell corresponding to the mapped and arranged position to indicate that the first unit cell has been mapped and arranged with the chiplet.
3. The method according to claim 1, wherein when confirming a mapped and arranged position of the chiplet to be mapped and arranged on the first unit cell on the topology where a mapped and arranged position of a chiplet has not been confirmed, a mapped and arranged position at which a least increase in communication power consumption occurs after being so mapped and arranged is selected as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation based on a communication relationship between the chiplet with a confirmed mapped and arranged position and a chiplet to be mapped and arranged.
4. The method according to claim 3, to select a mapped and arranged position at which a least increase in communication power consumption occurs after being so mapped and arranged as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation based on a communication relationship between the chiplet with a confirmed mapped and arranged position and a chiplet to be mapped and arranged, the following steps are implemented: determining all mappable and arrangeable positions of the chiplet to be mapped and arranged; calculating an increased communication power consumption of the chiplet to be mapped and arranged after being mapped and arranged at each mappable and arrangeable position; and selecting a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
5. The method according to claim 4, wherein the determining all mappable and arrangeable positions of the chiplet to be mapped and arranged comprises: dividing the chiplet to be mapped and arranged into a number of second unit cells each having a same dimension as the first unit cell; selecting a second unit cell in an upper left corner of the chiplet as a marking point, wherein the marking point of the chiplet being set on a first unit cell indicates that the first unit cell is the mapped and arranged position of the chiplet on the topology; performing a comparison and calculation on the first unit cell where a chiplet has not been confirmed to be mapped and arranged in order to select all first unit cells satisfying a first condition as all the mappable and arrangeable positions, where the first condition is: each of ranges enclosed by a length of a right side L and a length of a lower side W of the first unit cell is located within the topology, and in each of the ranges enclosed by a length of a right side L and a length of a lower side W of the first unit cell, no mapped and arranged chiplet has been confirmed, where L is a length of the chiplet, and W is a width of the chiplet.
6. The method according to claim 4, further comprising: when selecting a mappable and arrangeable position corresponding to an increased communication power consumption of a minimum value as the mapped and arranged position of the chiplet to be mapped and arranged for confirmation, the following steps are implemented when there are at least two mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value: calculating a minimum value of an increased communication power consumption of next chiplet to be mapped and arranged after being mapped and arranged when a current chiplet to be mapped and arranged is mapped and arranged at each of the mappable and arrangeable positions corresponding to the increased communication power consumption of the minimum value; selecting a mappable and arrangeable position corresponding to the increased communication power consumption of the minimum value of the chiplet to be mapped and arranged after being mapped and arranged, for which the increased communication power consumption of the next chiplet to be mapped and arranged after being mapped and arranged has a smaller minimum value, as a mapped and arranged position of the chiplet to be mapped and arranged for confirmation.
7. The method according to claim 4, wherein a side length of the first unit cell is a common divisor of lengths and widths of the theoretical values of the dimensions of all the chiplets, and the determining all mappable and arrangeable positions of the chiplet to be mapped and arranged comprises determining respectively all mappable and arrangeable positions of the chiplet to be mapped and arranged when being placed laterally and all mappable and arrangeable positions of the chiplet to be mapped and arranged when being placed longitudinally.
8. The method according to any one of claims 1 to 7, wherein a side length of the first unit cell is the greatest common divisor of lengths and widths of the theoretical values of the dimensions of all the chiplets.
9. An electronic device, including at least one processor and a memory communicatively connected to the at least one processor, wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform steps of the method of any one of claims 1 to 8.
10. A storage medium storing a computer program, wherein the program implements steps of the method of any one of claims 1 to 8 when executed by a processor.
LU503256A 2022-01-11 2022-12-27 2.5d chiplet arrangement method for optimizing communication power consumption LU503256B1 (en)

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