KR980006097A - Device isolation method of semiconductor device - Google Patents

Device isolation method of semiconductor device Download PDF

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Publication number
KR980006097A
KR980006097A KR1019960025800A KR19960025800A KR980006097A KR 980006097 A KR980006097 A KR 980006097A KR 1019960025800 A KR1019960025800 A KR 1019960025800A KR 19960025800 A KR19960025800 A KR 19960025800A KR 980006097 A KR980006097 A KR 980006097A
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South Korea
Prior art keywords
doped
groove
poly
forming
film
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KR1019960025800A
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Korean (ko)
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이찬용
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김주용
현대전자산업 주식회사
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Priority to KR1019960025800A priority Critical patent/KR980006097A/en
Publication of KR980006097A publication Critical patent/KR980006097A/en

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Abstract

본 발명은 반도체 소자의 소자분리방법에 관한 것으로, 반도체 소자의 소자분리방식에 있어서 실리콘 기판 상부에 증착된 질화막을 식각 마스크를 사용하여 질화막 패턴을 형성한 다음, 상기 질화막 패턴을 마스크로 사용하여 실리콘 기판을 일정 깊이로 식각하여 홈을 형성하고, 상기 형성된 홈에 소자 분리를 위하여 Doped-Poly를 증착한후, 상기 홈에 절연막을 채우고 홈이외의 부분에 존재하는 절연막을 제거하는 공정을 포함함으로써, 반도체 소자의 소자 분리 제조 방법소자간에 존재하는 누설전류를 효과적으로 최소화하여 소자의 리프레쉬 시간을 보장할 수 있으며, 최소 간격의 소자 분리가 가능하여 고집적 반도체 소자에 적용 가능하다.The present invention relates to a device isolation method for a semiconductor device, which comprises forming a nitride film pattern on a nitride film deposited on a silicon substrate by using an etching mask in a device isolation method of a semiconductor device, Forming a groove by etching the substrate to a predetermined depth, depositing doped-poly for element isolation in the formed groove, filling the groove with the insulating film, and removing the insulating film existing in a portion other than the groove, Method for Manufacturing Device Separation of Semiconductor Device Leakage current existing between devices can be minimized effectively to ensure a refresh time of the device, device separation can be performed with minimum spacing, and it is applicable to highly integrated semiconductor devices.

Description

반도체 소자의 소자분리 방법Device isolation method of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2e도는 본 발명의 기술에 따른 반도체 소자의 소자분리 제조 공정도이다.Figs. 2a to 2e are device isolation fabrication process diagrams of a semiconductor device according to the technique of the present invention.

Claims (9)

반도체 기판상부에 산화막과 질화막을 차례로 형성하는 공정과 상기 질화막위에 소자분리용 마스크를 이용한 감광막 패턴을 형성하는 공정과 상기 감광막패턴을 마스크로하여 상기 희생용 절연막 패턴을 형성하는 공정과 하부에 존재하는 실리콘 기판을 일정깊이로 식각하여 홈을 형성하는 공정과 상기 형성된 홈에 소자 분리를 위하여 Doped-Poly를 증착하는 공정과, 상기 홈에 소자분리 절연 산화막을 채우고 상기 홈 이외의 부분에 존재하는 절연 산화막을 제거하는 공정을 포함하는 것을 특징으로하는 반도체 소자의 소자 분리방법.A step of forming an oxide film and a nitride film on the semiconductor substrate in order, a step of forming a photoresist pattern using the element separation mask on the nitride film, a step of forming the sacrificial insulation film pattern using the photoresist pattern as a mask, A step of forming a trench by etching a silicon substrate to a predetermined depth, a step of depositing doped-poly for element isolation in the formed trench, a step of filling an element isolation insulating oxide film in the trench and forming an insulating oxide film And a step of removing the semiconductor element. 제1항에 있어서 Doped-Poly를 측벽에만 형성시키는 것을 특징으로 하는 반도체 소자의 소자분리방법.The method according to claim 1, wherein the doped-poly is formed only on the sidewall. 제1항에 있어서 상기 홈의 측벽을 경사지게 형성한후 Doped-Poly를 증착하는 특징으로 하는 반도체 소자의 소자분리방법.The device isolation method according to claim 1, wherein a side wall of the groove is formed obliquely and then doped-poly is deposited. 제1항에 있어서 상기 Doped-Poly를 증착한후 측벽의 실리콘 속으로 자동 도핑된 후에 다시 Doped-Poly를 제거하는 것을 특징으로하는 반도체 소자의 소자분리방법.The method of claim 1, wherein after the doped-poly is deposited, the doped-poly is automatically doped into the silicon of the side wall, and then the doped-poly is removed. 제1항에 있어서 상기 홈에 절연막을 채우고 홈이외의 부분에 존재하는 절연막들을 제거할 때 CMP 방법을 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 소자분리방법.The method according to claim 1, wherein the groove is filled with an insulating film and the insulating films existing in portions other than the groove are removed using a CMP method. 반도체 기판상부에 산화막과 질화막을 차례로 형성하는 공정과 상기 질화막위에 소자분리용 마스크를 이용한 감광막 패턴을 형성하는 공정과, 상기 감광막 패턴을 마스크로하여 상기 절화막을 식각하여 질화막 패턴을 형성하는 공정과, 감광막을 제거한 후에 상기 질화막 패턴을 마스크로 사용하여 실리콘 기판을 일정 깊이로 식각하여 홈을 형성하는 공정과 상기 형성된 홈에 소자 분리를 위하여 Doped-Poly를 측벽에만 형성시키는 공정과, 상기 홈에 절연막을 채우고 홈이외의 부분에 존재하는 절연막을 제거하는 공정을 포함하는 반도체 소자의 분리 제조 방법.A step of forming an oxide film and a nitride film on the semiconductor substrate in order, a step of forming a photoresist pattern using the element separation mask on the nitride film, a step of forming a nitride film pattern by etching the cut film using the photoresist pattern as a mask, A step of forming a groove by etching the silicon substrate to a predetermined depth by using the nitride film pattern as a mask after removing the photoresist film, a step of forming a doped-poly only on the sidewall for element isolation in the formed groove, And removing the insulating film existing in portions other than the groove. 제6항에 있어서 상기 홈의 측벽을 경사지게 형성한후 Doped-Poly를 사용하는 반도체 소자의 소자 분리 방법.The method of claim 6, wherein the groove is sloped and then the doped-poly is used. 제6항에 있어서 소자 분리 영역이 작아짐에 따라 Doped-Poly를 증착한후 측벽의 실리콘 속으로 자동 Doping시킨후에 다시 Doped-Poly를 제거하는 소자 분리 방법.7. The device isolation method according to claim 6, wherein the doped-poly is deposited as the device isolation region becomes smaller, and then the doped-poly is removed again after the doped-poly is automatically doped into the silicon of the side wall. 제6항에 있어서 상기 홈에 절연막을 채우고 홈이외의 부분에 존재하는 절연막들을 제거할 때 CMP 방법을 이용하여 제거하는 것을 특징으로하는 반도체 소자의 소자분리방법.The method of claim 6, wherein the groove is filled with an insulating film and the insulating films existing in portions other than the groove are removed using a CMP method. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960025800A 1996-06-29 1996-06-29 Device isolation method of semiconductor device KR980006097A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59214238A (en) * 1983-05-20 1984-12-04 Sanyo Electric Co Ltd Formation of isolation region
JPS61112343A (en) * 1984-11-07 1986-05-30 Nec Corp Manufacture of semiconductor device
JPS6262516A (en) * 1985-09-13 1987-03-19 Hitachi Ltd Impurity diffusing method
JPS63186423A (en) * 1987-01-29 1988-08-02 Toshiba Corp Manufacture of semiconductor device
JPH05166919A (en) * 1991-12-18 1993-07-02 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59214238A (en) * 1983-05-20 1984-12-04 Sanyo Electric Co Ltd Formation of isolation region
JPS61112343A (en) * 1984-11-07 1986-05-30 Nec Corp Manufacture of semiconductor device
JPS6262516A (en) * 1985-09-13 1987-03-19 Hitachi Ltd Impurity diffusing method
JPS63186423A (en) * 1987-01-29 1988-08-02 Toshiba Corp Manufacture of semiconductor device
JPH05166919A (en) * 1991-12-18 1993-07-02 Mitsubishi Electric Corp Semiconductor device and manufacture thereof

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