KR980005528A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDF

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Publication number
KR980005528A
KR980005528A KR1019960024291A KR19960024291A KR980005528A KR 980005528 A KR980005528 A KR 980005528A KR 1019960024291 A KR1019960024291 A KR 1019960024291A KR 19960024291 A KR19960024291 A KR 19960024291A KR 980005528 A KR980005528 A KR 980005528A
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KR
South Korea
Prior art keywords
film
forming
titanium
nitride film
titanium nitride
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KR1019960024291A
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Korean (ko)
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KR100220947B1 (en
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신찬수
홍미란
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김주용
현대전자산업 주식회사
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Priority to KR1019960024291A priority Critical patent/KR100220947B1/en
Publication of KR980005528A publication Critical patent/KR980005528A/en
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Publication of KR100220947B1 publication Critical patent/KR100220947B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 반도체기판에 불순물 접합영역을 형성하고, 전체표면상부에 층간절연막을 형성한 다음, 콘택마스크를 이용하여 상기 층간절연막을 식각함으로써 상기 불순물 접합영역을 노출시키는 콘택홀을 형성하고 확산방지막을 형성하는 반도체소자의 금속배선 형성방법에 있어서, 상기 불순물 접합영역에 접속되도록 전체표면상부에 티타늄막을 소정두께 형성하고 상기 티타늄막의 상측 일정두께를 티타늄질화막으로 형성화되는 동시에 상기 티타늄막과 반도체기판의 계명에 실리콘티타늄막을 형성하는 제1열처리공정을 실시한 다음, 상기 티타늄질화막에 산소를 충진시켜 티타늄산화질화막을 형성하는 제2열처리공정으로 실리콘티타튬/티타늄막/티타늄산화질화막 적층구조의 확산방지막을 형성하되, 하나의 증착챔버와 RTP 만을 이용하여 공정단가를 절감하고 콘택저항을 낮출 수 있어 반도체소자의 특성 및 신뢰성을 향상시키고 반도체소자의 생산성 및 수율을 향상시키며 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.An impurity junction region is formed in a semiconductor substrate, an interlayer insulating film is formed on the entire surface of the semiconductor substrate, and then the interlayer insulating film is etched by using a contact mask, Forming a titanium nitride film on the entire surface of the semiconductor substrate so as to be connected to the impurity junction region and forming a titanium nitride film on the upper side of the titanium film to a predetermined thickness; Forming a titanium oxide film on the titanium nitride film and forming a titanium oxide nitride film on the titanium nitride film by performing a first heat treatment step of forming a titanium nitride film on the titanium film and a semiconductor substrate, A diffusion barrier film of a film / titanium oxide nitride film laminated structure is formed By using only one deposition chamber and RTP, it is possible to reduce the process cost and reduce the contact resistance, thereby improving the characteristics and reliability of the semiconductor device, improving the productivity and yield of the semiconductor device, and enabling high integration of the semiconductor device. Technology.

Description

반도체 소자의 금속배선 형성방법METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1a도 내지 제1d도는 본 발명의 실시예에 따른 반도체소자의 금속배선 형성방법을 도시한 단면도.FIGS. 1A to 1D are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention; FIGS.

Claims (4)

반도체기판에 불순물 접합영역을 형성하고, 전체표면상부에 층간절연막을 형성한 다음, 콘택마스크를 이용하여 상기 층간절연막을 식각함으로써 상기 불순물 접합영역을 노출시키는 콘택홀을 형성하고 확산방지막을 형성하는 반도체소자의 금속배선 형성방법에 있어서, 상기 불순물 접합영역에 접속되도록 전체표면상부에 티타늄막을 소정두께 형성하는 공정과, 상기 티타늄막의 상측 일정두께를 티타늄질화막으로 형성화되는 동시에 상기 티타늄막과 반도체기판의 계명에 실리콘티타늄막을 형성하는 제1열처리공정을 실시하는 공정과, 상기 티타늄질화막에 산소를 증진시켜 티타늄산화 질화막을 형성하는 제2열처리공정으로 실리콘티타늄막/티타늄막/티타늄산화질화막 적층구조의 확산방지막을 형성하는 공정을 포함하는 반도체소자의 금속배선 형성방법.Forming an impurity junction region in a semiconductor substrate, forming an interlayer insulating film on the entire surface, etching the interlayer insulating film using a contact mask to form contact holes exposing the impurity junction regions, A method of forming a metal wiring of a device, comprising the steps of: forming a predetermined thickness of a titanium film on an entire surface to be connected to the impurity junction region; forming a titanium nitride film on the upper side of the titanium film, A step of performing a first heat treatment step of forming a titanium titanium oxide film on the titanium nitride film and a titanium oxide film on the titanium nitride film by a second heat treatment step of forming titanium nitride oxide film by increasing oxygen in the titanium nitride film, And a step of forming a metal film The method of forming. 제1항에 있어서, 상기 티타늄막은 CVD 또는 PVD 방법으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the titanium film is formed by CVD or PVD. 제1항에 있어서, 상기 제1열처리공정은 600 ~ 850℃ 온도 정도의 RTP 에서 암모니아가스와 아르곤가스를 플로우시키며 1 ~70 초 동안 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the first annealing process is performed for 1 to 70 seconds by flowing ammonia gas and argon gas in RTP at a temperature of 600 to 850 ° C. 제1항에 있어서, 상기 제2열처리공정은 500 ~700℃ 온도 정도의 RTP 에서 산소가스와 아르곤가스를 플로우시키며 1 ~70 초 동안 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법.The method according to claim 1, wherein the second heat treatment is performed for 1 to 70 seconds by flowing oxygen gas and argon gas in RTP at a temperature of 500 to 700 ° C. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024291A 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device KR100220947B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024291A KR100220947B1 (en) 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device

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Application Number Priority Date Filing Date Title
KR1019960024291A KR100220947B1 (en) 1996-06-27 1996-06-27 Forming method for metal wiring of semiconductor device

Publications (2)

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KR980005528A true KR980005528A (en) 1998-03-30
KR100220947B1 KR100220947B1 (en) 1999-09-15

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