KR970076764A - Matrix Control Circuit Using KBPS Data of Voice Multiple VCR - Google Patents
Matrix Control Circuit Using KBPS Data of Voice Multiple VCR Download PDFInfo
- Publication number
- KR970076764A KR970076764A KR1019960018927A KR19960018927A KR970076764A KR 970076764 A KR970076764 A KR 970076764A KR 1019960018927 A KR1019960018927 A KR 1019960018927A KR 19960018927 A KR19960018927 A KR 19960018927A KR 970076764 A KR970076764 A KR 970076764A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- voice
- detector
- carrier
- unit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/60—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals
- H04N5/607—Receiver circuitry for the reception of television signals according to analogue transmission standards for the sound signals for more than one sound signal, e.g. stereo, multilanguages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/08—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division
- H04N7/084—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the horizontal blanking interval only
- H04N7/085—Systems for the simultaneous or sequential transmission of more than one television signal, e.g. additional information signals, the signals occupying wholly or partially the same frequency band, e.g. by time division with signal insertion during the horizontal blanking interval only the inserted signal being digital
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Circuits Of Receivers In General (AREA)
- Television Receiver Circuits (AREA)
- Stereo-Broadcasting Methods (AREA)
Abstract
본 발명은 KBPS수신 데이터를 디코딩하여 음성 다중방송방식을 판단할 수 있는 음성 다중 VCR의 매트릭스 제어회로에 관한 것으로서, 전계강도가 약하거나 수신상태가 불량한 난시청 지역에서도 음성 다중 방송방식을 확실하게 검출할 수 있게 하기 위한 것이다.The present invention relates to a matrix control circuit of a voice multiplexing VCR capable of deciding the voice multicasting method by decoding KBPS received data. It is to be able to.
이를 위하여 본 발명은 안테나로부터 수신되는 복합채널의 고주파(RF)신호로부터 원하는 채널을 동조시키는 주파수 동조부; 상기 주파수 동조부에서 동조된 채널신호로부터 음성신호에 대한 중간주파수 신호(SIF)만을 추출하는 SIF검파부; 상기 SIF검파부에서 추출된 음성 중간 주파수 신호중 제1반송파와 제2반송파에 실려 들어오는 음성신호를 추출하는 제1반송파 검파부 및 제2반송파 검파부; KBPS 데이터를 디코딩하는 KBPS 디코딩부; 상기 KBPS 디코딩부를 거쳐 복호화된 검출정보를 입력받아 스테레오 방송이나 모노 방송 또는 2개국어 동시 방송 처리를 위한 각종 제어동작을 수행하는 마이크로 프로세서; 상기 마이크로 프로세서의 제어에 따라 스위칭 신호를 변화시키는 파일럿 비트 검출부; 상기 파일럿 비트 검출부의 스위칭 신호에 따라 상기2개의 반송파 검파부의 출력을 스위칭하거나 가산/감산 제어하여 각 L, R 채널의 실제 음성출력신호를 합성해내는 매트리스 회로부; 상기 매트릭스 회로부에서 합성되는 음성신호를 증폭하여 각각의 스피커를 통해 외부로 출력하는 제1음성 출력부 및 제2음성 출력부로 구성함을 특징으로 한다.To this end, the present invention provides a frequency tuning unit for tuning a desired channel from a high frequency (RF) signal of a complex channel received from an antenna; A SIF detector for extracting only an intermediate frequency signal (SIF) for a voice signal from the channel signal tuned by the frequency tuner; A first carrier detector and a second carrier detector for extracting voice signals carried on a first carrier and a second carrier among voice intermediate frequency signals extracted by the SIF detector; A KBPS decoding unit for decoding KBPS data; A microprocessor which receives the decoded detection information through the KBPS decoding unit and performs various control operations for stereo broadcasting, mono broadcasting or bilingual simultaneous broadcasting; A pilot bit detector for changing a switching signal according to the control of the microprocessor; A mattress circuit unit configured to synthesize or output real voice output signals of respective L and R channels by switching or adding / subtracting the outputs of the two carrier detectors according to the switching signal of the pilot bit detector; And a first audio output unit and a second audio output unit for amplifying the voice signal synthesized by the matrix circuit unit and outputting the audio signal to the outside through each speaker.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 2캐리어 방식 음성 다중방송 수신 및 처리회로에서 KBPS 수신 데이터를 이용한 매트릭스 제어회로의 일 실시예를 보인 블럭도, 제3도는 본 발명에서 사용하기 위한 KBPS 수신 데이터의 한 예를 보이고 있는 참고표이다.FIG. 2 is a block diagram showing an embodiment of a matrix control circuit using KBPS received data in a 2-carrier voice multicast reception and processing circuit according to the present invention. FIG. 3 is an example of KBPS received data for use in the present invention. This is a reference table.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960018927A KR0174209B1 (en) | 1996-05-31 | 1996-05-31 | Matrix controlling circuit using kbps data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019960018927A KR0174209B1 (en) | 1996-05-31 | 1996-05-31 | Matrix controlling circuit using kbps data |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970076764A true KR970076764A (en) | 1997-12-12 |
KR0174209B1 KR0174209B1 (en) | 1999-04-15 |
Family
ID=19460306
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019960018927A KR0174209B1 (en) | 1996-05-31 | 1996-05-31 | Matrix controlling circuit using kbps data |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0174209B1 (en) |
-
1996
- 1996-05-31 KR KR1019960018927A patent/KR0174209B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0174209B1 (en) | 1999-04-15 |
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Payment date: 20071101 Year of fee payment: 10 |
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