KR970060399A - Method for planarizing semiconductor memory device - Google Patents

Method for planarizing semiconductor memory device Download PDF

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Publication number
KR970060399A
KR970060399A KR1019960002079A KR19960002079A KR970060399A KR 970060399 A KR970060399 A KR 970060399A KR 1019960002079 A KR1019960002079 A KR 1019960002079A KR 19960002079 A KR19960002079 A KR 19960002079A KR 970060399 A KR970060399 A KR 970060399A
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South Korea
Prior art keywords
forming
peripheral circuit
interlayer insulating
insulating film
wiring
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KR1019960002079A
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Korean (ko)
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KR0175043B1 (en
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박인선
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 메모리 장치의 평탄화 방법이 개시되어 있다. 본 발명은 셀 커패시터를 구비하는 메모리 셀이 2차원 적으로 배열된 셀 어레이 영역과 상기 메모리 셀을 구동시키기 위한 집적회로로 이루어진 주변회로 영역을 구비하는 반도체 메모리 장치의 평탄화 방법에 있어서, 상기 셀 어레이 영역과 상기 주변회로 영역에 각각 동일한 높이를 가지는 셀 커페시터와 제1배선을 동시에 형성하고, 상기 셀 커패시터와 상기 제1배선이 형성된 기판 전체를 덮는 제2층간절연막을 형성함으로써, 상기 셀 어레이 영역과 상기 주변회로 영역 사이의 경계 부분에서 제2층간절연막이 경사면을 갖지 않도록 형성하는 것을 특징으로 한다. 본 발명에 의하면, 평평한 제2층간절연막을 형성할 수 있어 그 위에 제2배선을 형성할 때 패턴불량이 발생하는 것을 방지할 수 있다.A planarizing method of a semiconductor memory device is disclosed. There is provided a method of planarizing a semiconductor memory device having a cell array region in which memory cells having cell capacitors are two-dimensionally arranged and a peripheral circuit region formed of an integrated circuit for driving the memory cells, Forming a cell capacitor and a first wiring at the same height in the peripheral circuit region and the peripheral circuit region at the same time and forming a second interlayer insulating film covering the entire substrate on which the cell capacitor and the first wiring are formed, And the second interlayer insulating film is formed so as not to have an inclined surface at a boundary portion between the peripheral circuit regions. According to the present invention, it is possible to form a flat second interlayer insulating film and to prevent a pattern defect from occurring when the second wiring is formed thereon.

Description

반도체 메모리 장치의 평탄화 방법Method for planarizing semiconductor memory device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 내지 제4도는 본 발명의 평탄화 방법을 설명하기 위한 단면도이다.FIGS. 2 to 4 are cross-sectional views for explaining the planarization method of the present invention.

Claims (7)

하나의 셀 커패시터와 하나의 트랜지스터로 이루어지는 메모리 셀이 2차원적으로 배열된 셀 어레이 영역 및 상기 메모리 셀을 구동시키기 위한 집적회로로 이루어지는 주변회로 영역을 구비하는 반도체 메모리 장치의 평탄화 방법에 있어서, 반도체기판 상에 제1층간절연막을 형성하는 단계; 상기 제1층간절연막을 패터닝하여 상기 셀 어레이 영역 및 상기 주변회로 영역에 각각 상기 셀 커패시터의 축적전극 콘택홀 및 제1배선 콘택홀을 구비하는 제1층간절연막 패턴을 형성하는 단계; 상기 결과물 전면에 상기 축적전극 콘택홀 및 상기 제1배선콘택홀을 채우는 제1도전막을 형성하는 단계; 상기 제1도전막을 패터닝하여 상기 축적전극 콘택홀을 덮는 축적전극 및 상기 주변회로 영역 전체를 덮는 제1도전막 패턴을 형성하는 단계; 상기 결과물 전면에 유전막 및제2도전막을 차례로 형성하는 단계; 상기 셀 어레이 영역과 상기 주변회로 영역을 격리시키면서 상기 주변회로영역 내에 국부적인 배선을 형성하기 위하여 상기 제1도전막, 상기 유전막, 및 상기 제1도전막 패턴을 연속적으로 패터닝함으로써 상기 셀 어레이 영역에 상기 제2 도전막으로 이루어진 플레이트 전극, 유전막 패턴, 및 제1도전막 패턴으로 이루어진 더미 패턴을 형성함과 동시에 상기 주변회로 영역에 제1배선을 형성하는 단계; 및 상기 결과물 전면에 제2층간절연막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.1. A method of planarizing a semiconductor memory device comprising a cell array region in which memory cells each consisting of one cell capacitor and one transistor are two-dimensionally arranged and a peripheral circuit region comprising an integrated circuit for driving the memory cell, Forming a first interlayer insulating film on a substrate; Forming a first interlayer insulating film pattern including storage electrode contact holes and first wiring contact holes of the cell capacitor in the cell array region and the peripheral circuit region by patterning the first interlayer insulating film; Forming a first conductive film on the entire surface of the resultant to fill the storage electrode contact hole and the first wiring contact hole; Forming a first conductive film pattern covering the entire peripheral circuit region and storage electrodes covering the storage electrode contact holes by patterning the first conductive film; Sequentially forming a dielectric layer and a second conductive layer on the entire surface of the resultant structure; The first conductive film, the dielectric film, and the first conductive film pattern are successively patterned to isolate the cell array region and the peripheral circuit region while forming a local wiring in the peripheral circuit region, Forming a dummy pattern composed of the plate electrode, the dielectric film pattern, and the first conductive film pattern of the second conductive film, and forming a first wiring in the peripheral circuit area; And forming a second interlayer insulating film on the entire surface of the resultant structure. 제1항에 있어서, 상기 제1층간절연막 패턴은 BPSG막으로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 편탄화 방법.The method of claim 1, wherein the first interlayer insulating film pattern is formed of a BPSG film. 제1항에 있어서, 상기 제1도전막은 도우핑된 폴리실리콘막 및 내산화성 금속막중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.The flattening method of claim 1, wherein the first conductive layer is formed of any one of a doped polysilicon layer and an oxidation-resistant metal layer. 제3항에 있어서, 상기 내산화성 금속막은 백금, 질화 텅스텐, 및 질화 타이타늄으로 이루어진 일 군중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.The flattening method of claim 3, wherein the oxidation-resistant metal film is formed of one selected from the group consisting of platinum, tungsten nitride, and titanium nitride. 제1항에 있어서, 상기 유전막은 탄탈륨산화막 및 BST막중 선택된 어느 하나로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.The flattening method of claim 1, wherein the dielectric layer is formed of a tantalum oxide layer or a BST layer. 제1항에 있어서, 상기 제2층간절연막은 BPSG막으로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.The flattening method of a semiconductor memory device according to claim 1, wherein the second interlayer insulating film is formed of a BPSG film. 제1항에 있어서, 상기 더미 패턴 및 이와 인접한 제1배선 사이의 간격은 최소 디자인 룰의 크기로 형성하는 것을 특징으로 하는 반도체 메모리 장치의 평탄화 방법.The flattening method of a semiconductor memory device according to claim 1, wherein a distance between the dummy pattern and the first wiring adjacent thereto is formed to a size of a minimum design rule. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960002079A 1996-01-30 1996-01-30 Planarization Method of Semiconductor Memory Device KR0175043B1 (en)

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