KR970058243A - Data Transceiver Over Redundant Buses - Google Patents
Data Transceiver Over Redundant Buses Download PDFInfo
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- KR970058243A KR970058243A KR1019950059464A KR19950059464A KR970058243A KR 970058243 A KR970058243 A KR 970058243A KR 1019950059464 A KR1019950059464 A KR 1019950059464A KR 19950059464 A KR19950059464 A KR 19950059464A KR 970058243 A KR970058243 A KR 970058243A
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Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
이중화의 버스 모듈 유럽 버스로 데이타를 송수신하는 장치에 관한 것이다.Redundant bus module The present invention relates to a device for transmitting and receiving data on a European bus.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
이중화로 구현된 VME Bus로 두개의 주장치가 동시에 종속장치들을 억세스하도록 하며, 이중화의 VME Bus와 접속된 두개의 주장치에서 한쪽 주장치가 비 정상적일 경우 상대편 마스터에서 이중화된 VME Bus를 모두 관장하도록 하여 부하 분담을 주는 이중화된 버스를 통한 데이타 송수신 장치를 제공한다.Redundant VME Bus allows two main units to access slave devices at the same time, and if two main units connected to the redundant VME bus are abnormal, one master unit manages all redundant VME buses from the other master. Provides a data transmission and reception device through a redundant bus giving a sharing.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
이중화로 구현되어 데이타를 송수신하기 위한 제1버스 및 제2버스를 이용하는 장치는 어드레스디코더부, 상기 제1버스와 접속된 제1어드레스버퍼부 및 제1데이타버퍼부, 상기 제2버스와 접속된 제2어드레스버퍼부 및 제2데이타버퍼부를 구비하며, 상기 어드레스디코더부에 제1신호 및 제2신호를 입력하며, 상기 제1신호의 활성화에 의해 상기 제1어드레스버퍼부 및 제1데이타버퍼부가 동작하여 상기 제1버스를 점유하며, 상기 제2신호가 활성화에 의해 상기 제2어드레스버퍼수단 및 제2데이타버퍼수단이 동작하여 상기 제2버스 점유하는 제1주장치와, 상기 제1주장치와 이중화로 구현되며, 상기 제1주장치의 제1신호가 활성화일 시 상기 제2신호가 활성화가 되며, 상기 제1주장치의 제2신호가 활성화일 시 상기 제1신호가 활성화가 되며, 상기 제1주장치의 제1신호 및 제2신호가 비활성화일시 상기 제1신호 및 상기 제2신호가 활성화가 되는 제2주장치와, 상기 제1버스를 점유한 주장치에 의해 상기 데이타를 송수신하며, 상기 제1버스와 접속된 다수의 제1종속장치와, 상기 제2버스를 점유한 주장치에 의해 상기 데이타를 송수신하며, 상기 제2버스와 접속된 다수의 제2종속장치로 구성한다.An apparatus using a first bus and a second bus for transmitting and receiving data, which is implemented in redundancy, includes an address decoder unit, a first address buffer unit and a first data buffer unit connected to the first bus, and a second bus connected to the second bus. A second address buffer part and a second data buffer part, and input a first signal and a second signal to the address decoder part, and by activating the first signal, the first address buffer part and the first data buffer part A first main device which is operative to occupy the first bus, and wherein the second address buffer means and a second data buffer means are operated to occupy the second bus by activating the second signal; The second signal is activated when the first signal of the first main device is activated, and the first signal is activated when the second signal of the first main device is activated, and the first main device is activated. Of The first and second signals are deactivated when the first and second signals are deactivated, and the data is transmitted and received by the main device occupying the first bus and connected to the first bus. A plurality of first slave devices and a main device occupying the second bus transmit and receive the data, and constitute a plurality of second slave devices connected to the second bus.
4. 발명의 중요한 용도4. Important uses of the invention
교환기에서 VME버스를 효율적으로 이용하기 위해 이중화하기 위해 이를 구현한다.Implement this for redundancy in order to use the VME bus efficiently at the exchange.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따라 이중화된 버스를 통해 통신하는 장치의 시스템블럭도를 나타내는 도면,2 is a system block diagram of an apparatus for communicating over a redundant bus in accordance with the present invention;
제3도는 본 발명에 따라 이중화된 버스를 억세스를 위한 주장치의 시스템블럭도를 나타내는 도면3 shows a system block diagram of a main device for accessing a redundant bus in accordance with the present invention.
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950059464A KR970058243A (en) | 1995-12-27 | 1995-12-27 | Data Transceiver Over Redundant Buses |
Applications Claiming Priority (1)
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KR1019950059464A KR970058243A (en) | 1995-12-27 | 1995-12-27 | Data Transceiver Over Redundant Buses |
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KR970058243A true KR970058243A (en) | 1997-07-31 |
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KR1019950059464A KR970058243A (en) | 1995-12-27 | 1995-12-27 | Data Transceiver Over Redundant Buses |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01196936A (en) * | 1988-02-01 | 1989-08-08 | Toshiba Corp | Bus type duplicated transmission equipment |
JPH02278935A (en) * | 1989-04-19 | 1990-11-15 | Hitachi Cable Ltd | Duplicating system for bus type network |
KR950013295A (en) * | 1993-10-12 | 1995-05-17 | 정장호 | Redundancy system |
KR950016418A (en) * | 1993-11-17 | 1995-06-17 | 박성규 | Bus redundancy control of multiple processors sharing common bus resources and recovery method in the event of a bus fault condition |
KR950030719A (en) * | 1994-04-13 | 1995-11-24 | 박성규 | Device that duplicates communication bus |
-
1995
- 1995-12-27 KR KR1019950059464A patent/KR970058243A/en not_active IP Right Cessation
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01196936A (en) * | 1988-02-01 | 1989-08-08 | Toshiba Corp | Bus type duplicated transmission equipment |
JPH02278935A (en) * | 1989-04-19 | 1990-11-15 | Hitachi Cable Ltd | Duplicating system for bus type network |
KR950013295A (en) * | 1993-10-12 | 1995-05-17 | 정장호 | Redundancy system |
KR950016418A (en) * | 1993-11-17 | 1995-06-17 | 박성규 | Bus redundancy control of multiple processors sharing common bus resources and recovery method in the event of a bus fault condition |
KR950030719A (en) * | 1994-04-13 | 1995-11-24 | 박성규 | Device that duplicates communication bus |
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