KR970058097A - TD bus test method of electronic exchange - Google Patents

TD bus test method of electronic exchange Download PDF

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Publication number
KR970058097A
KR970058097A KR1019950061454A KR19950061454A KR970058097A KR 970058097 A KR970058097 A KR 970058097A KR 1019950061454 A KR1019950061454 A KR 1019950061454A KR 19950061454 A KR19950061454 A KR 19950061454A KR 970058097 A KR970058097 A KR 970058097A
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KR
South Korea
Prior art keywords
bus
device block
block
address
cpu
Prior art date
Application number
KR1019950061454A
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Korean (ko)
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KR0183196B1 (en
Inventor
이진호
Original Assignee
정장호
Lg 정보통신 주식회사
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Application filed by 정장호, Lg 정보통신 주식회사 filed Critical 정장호
Priority to KR1019950061454A priority Critical patent/KR0183196B1/en
Publication of KR970058097A publication Critical patent/KR970058097A/en
Application granted granted Critical
Publication of KR0183196B1 publication Critical patent/KR0183196B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/20—Testing circuits or apparatus; Circuits or apparatus for detecting, indicating, or signalling faults or troubles

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Monitoring And Testing Of Exchanges (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

본 발명은 전자교환기에 대한 것으로, 프로세서 블럭과 디바이스 블럭간에 데이타를 주고받는 TD버스의 정상 동작여부를 효율적으로 테스트하도록 하는 전자교환기의 TD버스 테스트 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic exchange, and more particularly, to a TD bus test method of an electronic exchange for efficiently testing the normal operation of a TD bus that exchanges data between a processor block and a device block.

종래의 방식으로 TD버스를 테스트 하는 경우 CPU(11)가 모드정보, 데이타 및 어드레스를 디바이스 블럭(20)측으로 전송한 후 다시 모드정보와 어드레스를 디바이스 블럭(20)으로 출력하여 디바이스 블럭(20)으로부터 인가되는 데이타를 수신하여, 디바이스 블럭(20)측으로 출력했던 데이타와 자신이 수신한 데이타가 일치하는 지의 여부를 확인함으로써 TD버스의 정상여부를 테스트하는 바, 이와 같이 TD버스를 테스트하는 경우 CPU(11)가 디바이스 블럭(20)을 2회에 걸쳐 억세스하므로 TD버스 테스트시에 CPU(11)의 부하를 증가시키는 문제점이 있다.When the TD bus is tested in the conventional manner, the CPU 11 transmits the mode information, data, and address to the device block 20 side, and then outputs the mode information and address to the device block 20 to the device block 20. The TD bus is tested for normality by receiving data applied from the device and checking whether the data output to the device block 20 and the data received by the user are identical. Since 11 accesses the device block 20 twice, there is a problem of increasing the load of the CPU 11 during the TD bus test.

본 발명은 프로세서 블럭의 CPU가 디바이스 블럭측에 연결된 TD버스의 정상 여부를 테스트 하는 경우 CPU가 디바이스 블럭을 1회 억세스하여 TD버스를 테스트 하므로 TD버스 테스트시에 CPU에 걸리는 부하를 감소시키게 된다.The present invention reduces the load on the CPU during the TD bus test because the CPU of the processor block tests the TD bus by accessing the device block once when the CPU tests the TD bus connected to the device block.

Description

전자교환기의 TD버스 테스트 방법TD bus test method of electronic exchange

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 전자교환기의 TD버스 테스트 방식을 도시한 블럭도3 is a block diagram showing a TD bus test method of an electronic exchange according to the present invention.

Claims (1)

프로세서 블럭과 디바이스 블럭간에 연결된 TD버스의 정상 여부를 테스트하는 전자교환기의 TD버스 테스트 방법에 있어서, 상기 프로세서 블럭이 테스트 모드임을 나타내는 모드정보와, 어드레스를 상기 디바이스 블럭측으로 출력함과 동시에 상기 어드레스를 저장하는 제1과정과; 상기 제1과정 수행후 상기 디바이스 블럭이 상기 모드정보와 어드레스를 수신하는 경우 상기 어드레스를 복사하여 데이타 전송 타이밍에 데이타로서 상기 프로세서 블럭측으로 출력하는 제2과정과; 상기 제2과정 수행후 상기 프로세서 블럭이 디바이스 블럭으로부터 인가되는 데이타와 상기 저장한 어드레스를 비교하여 일치하는 지의 여부를 판단하고 일치여부에 따라 상기 TD버스의 정상 여부를 판정하는 제3과정을 포함하는 것을 특징으로 하는 전자교환기의 TD버스 테스트 방법.In a TD bus test method of an electronic exchange for testing whether a TD bus connected between a processor block and a device block is normal, mode information indicating that the processor block is in a test mode and an address are outputted to the device block and the address is simultaneously displayed. A first process of storing; A second step of copying the address and outputting the data to the processor block at the data transmission timing when the device block receives the mode information and the address after performing the first step; And a third step of determining whether the processor block is identical by comparing the data applied from the device block with the stored address after performing the second process, and determining whether the TD bus is normal according to whether the processor block matches. TD bus test method for an electronic exchange. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061454A 1995-12-28 1995-12-28 Td bus testing method of electronic switching system KR0183196B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950061454A KR0183196B1 (en) 1995-12-28 1995-12-28 Td bus testing method of electronic switching system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950061454A KR0183196B1 (en) 1995-12-28 1995-12-28 Td bus testing method of electronic switching system

Publications (2)

Publication Number Publication Date
KR970058097A true KR970058097A (en) 1997-07-31
KR0183196B1 KR0183196B1 (en) 1999-05-15

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ID=19445924

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950061454A KR0183196B1 (en) 1995-12-28 1995-12-28 Td bus testing method of electronic switching system

Country Status (1)

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KR (1) KR0183196B1 (en)

Also Published As

Publication number Publication date
KR0183196B1 (en) 1999-05-15

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