KR970053822A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Capacitor Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR970053822A
KR970053822A KR1019950052215A KR19950052215A KR970053822A KR 970053822 A KR970053822 A KR 970053822A KR 1019950052215 A KR1019950052215 A KR 1019950052215A KR 19950052215 A KR19950052215 A KR 19950052215A KR 970053822 A KR970053822 A KR 970053822A
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KR
South Korea
Prior art keywords
layer
conductive layer
metal silicide
insulating film
depositing
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KR1019950052215A
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Korean (ko)
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KR100192365B1 (en
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라관구
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문정환
Lg 반도체 주식회사
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Priority to KR1019950052215A priority Critical patent/KR100192365B1/en
Publication of KR970053822A publication Critical patent/KR970053822A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

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  • Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체 소자의 커패시터 제조방법에 관한 것으로, 커패시터 용량을 증가시킴은 물론 공정을 단수화하여 고집적소자 제작에 적합하도록 한 것이다.The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and to increase the capacity of the capacitor as well as to shorten the process to be suitable for manufacturing a highly integrated device.

본 발명에 따른 반도체 소자의 커패시터 제조방법은 게이트 절연막과 게이트 전극 및 불순물 영역이 각각 형성된 반도체 기판을 준비하는 단계; 상기 반도체 기판상에 제1절연막을 증착하는 단계; 상기 반도체 기판이 노출되도록 상기 제1절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제1절연막위에 제1도전층을 증착하고, 상기 제1도전층상에 금속실리사이드막을 증착하는 단계; 상기 금속실리사이드막을 대기분위기하에서 표면처리하여 표면을 울퉁불퉁하게 형성하는 단계; 상기 금속실리사이드막과 상기 제1도전층을 에치백하는 단계; 상기 금속실리사이드막을 포함한 상기 제1도전층의 노출된 표면위에 제2절연막을 증착하여 산화처리하는 단계; 상기 산화처리된 제2절연막위에 제2도전층을 형성하고, 상기 제2도전층과 제2절연막 및 제1도전층을 선택적으로 제거하는 단계를 포함하여 이루어진다.A method of manufacturing a capacitor of a semiconductor device according to the present invention includes preparing a semiconductor substrate having a gate insulating film, a gate electrode, and an impurity region, respectively; Depositing a first insulating film on the semiconductor substrate; Selectively removing the first insulating layer to expose the semiconductor substrate to form a contact hole; Depositing a first conductive layer on the first insulating layer including the contact hole and depositing a metal silicide layer on the first conductive layer; Surface-treating the metal silicide layer in an air atmosphere to form an uneven surface; Etching back the metal silicide layer and the first conductive layer; Depositing and oxidizing a second insulating film on the exposed surface of the first conductive layer including the metal silicide film; And forming a second conductive layer on the oxidized second insulating film, and selectively removing the second conductive layer, the second insulating film, and the first conductive layer.

Description

반도체 소자의 커패시터 제조방법Capacitor Manufacturing Method for Semiconductor Devices

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2a∼2f도는 본 발명에 따른 반도체 소자의 커패시터 제조공정도.2a to 2f is a process diagram of the capacitor manufacturing of the semiconductor device according to the present invention.

Claims (11)

게이트 절연막과 게이트 전극 및 불순물 영역된 각각 형성된 반도체 기판을 준비하는 단계; 상기 반도체 기판상에 제1절연막을 증착하는 단계; 상기 반도체 기판이 노출되도록 상기 제1절연막을 선택적으로 제거하여 콘택홀을 형성하는 단계; 상기 콘택홀을 포함한 상기 제1절연막위에 제1도전층을 증착하고, 상기 제1도전층상에 금속실리사이드막을 증착하는 단계; 상기 금속실리사이드막을 대기분위기하에서 표면처리하여 표면을 울퉁불퉁하게 형성하는 단계; 상기 금속실리사이드막과 상기 제1도전층을 에치백하는 단계; 상기 금속 실리사이드막을 포함한 상기 제1도전층의 노출된 표면위에 제2절연막을 증착하여 산화처리하는 단계; 상기 산화처리된 제2절연막위에 제2도전층을 형성하고, 상기 제2도전층과 제2절연막 및 제1도전층을 선택적으로 제거하는 단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.Preparing a semiconductor substrate each having a gate insulating film, a gate electrode, and an impurity region; Depositing a first insulating film on the semiconductor substrate; Selectively removing the first insulating layer to expose the semiconductor substrate to form a contact hole; Depositing a first conductive layer on the first insulating layer including the contact hole and depositing a metal silicide layer on the first conductive layer; Surface-treating the metal silicide layer in an air atmosphere to form an uneven surface; Etching back the metal silicide layer and the first conductive layer; Depositing and oxidizing a second insulating film on the exposed surface of the first conductive layer including the metal silicide film; And forming a second conductive layer on the oxidized second insulating film, and selectively removing the second conductive layer, the second insulating film, and the first conductive layer. . 제1항에 있어서, 상기 제1도전층은 다결정 실리콘을 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the first conductive layer uses polycrystalline silicon. 제1항에 있어서, 상기 금속실리사이드막은 텅스텐 실리사이드막(WSi2)을 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the metal silicide layer uses a tungsten silicide layer (WSi 2 ). 제1항에 있어서, 상기 금속실리사이드막의 표면처리는 U세+HF용액에 기판을 담그기(dipping)하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the surface treatment of the metal silicide layer is performed by dipping a substrate in a U-SE + HF solution. 제1항에 이어서, 상기 금속실리사이드막은 SF6와 N2가스를 이용하여 에치백하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the metal silicide layer is etched back using SF 6 and N 2 gases. 제1항에 이어서, 상기 금속실리사이드막과 제1도전층 제거시에 상기 금속실리사이드막을 울통한 부분만 남도록 제거하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the removal of the metal silicide layer and the first conductive layer is performed so that only a portion of the metal silicide layer remains intact. 제1항에 있어서, 제2절연막은 질화막을 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the second insulating film is a nitride film. 제1항에 있어서, 상기 제2도전층은 도우프드된 다결정 실리콘을 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the second conductive layer uses doped polycrystalline silicon. 제1항에 있어서, 상기 제1도전층은 스토리지 노드전극을 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the first conductive layer uses a storage node electrode. 제1항에 있어서, 상기 제2절연막은 커패시터 유전체막으로 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the second insulating layer is used as a capacitor dielectric layer. 제1항에 있어서, 상기 제2절연막은 커패시터 유전체막으로 사용하는 것을 특징으로 하는 반도체 소자의 커패시터 제조방법.The method of claim 1, wherein the second insulating layer is used as a capacitor dielectric layer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950052215A 1995-12-19 1995-12-19 Method for manufacturing capacitor of semiconductor device KR100192365B1 (en)

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KR1019950052215A KR100192365B1 (en) 1995-12-19 1995-12-19 Method for manufacturing capacitor of semiconductor device

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KR100192365B1 KR100192365B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203646A1 (en) * 2003-12-26 2008-08-28 Brother Kogyo Kabushiki Kaisha Image forming apparatus

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100548598B1 (en) * 1999-12-30 2006-02-02 주식회사 하이닉스반도체 Method for fabricating capacitor in semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080203646A1 (en) * 2003-12-26 2008-08-28 Brother Kogyo Kabushiki Kaisha Image forming apparatus
US8824952B2 (en) * 2003-12-26 2014-09-02 Brother Kogyo Kabushiki Kaisha Image forming apparatus

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