KR970053412A - Device Separation Method of Semiconductor Device - Google Patents

Device Separation Method of Semiconductor Device Download PDF

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Publication number
KR970053412A
KR970053412A KR1019950054960A KR19950054960A KR970053412A KR 970053412 A KR970053412 A KR 970053412A KR 1019950054960 A KR1019950054960 A KR 1019950054960A KR 19950054960 A KR19950054960 A KR 19950054960A KR 970053412 A KR970053412 A KR 970053412A
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KR
South Korea
Prior art keywords
pattern
nitride
film pattern
device isolation
forming
Prior art date
Application number
KR1019950054960A
Other languages
Korean (ko)
Inventor
박병준
Original Assignee
김주용
현대전자산업 주식회사
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950054960A priority Critical patent/KR970053412A/en
Publication of KR970053412A publication Critical patent/KR970053412A/en

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  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 반도체소자의 소자분리막 제조방법에 관한 것으로, 본 발명은 LOCOS 공정을 응용한 소자분리막 제조방법에 있어서, 반도체기판의 상부에 소자분리영역을 노출하는 제1질화막패턴과, 열산화막패턴, 제2질화막패턴을 차례로 형성하여 필드산화막 형성시 상기 열산화막패턴의 응축응력 성질을 이용하여 상기 제1질화막 패턴의 인장응력을 완화하므로써, 소자분리막을 용이하게 형성한다.The present invention relates to a device isolation film manufacturing method of a semiconductor device, the present invention relates to a device isolation film manufacturing method applying a LOCOS process, the first nitride film pattern for exposing the device isolation region on the semiconductor substrate, a thermal oxide film pattern, By forming the second nitride film pattern in sequence to reduce the tensile stress of the first nitride film pattern by using the condensation stress property of the thermal oxide film pattern, the device isolation film is easily formed.

Description

반도체소자의 소자분리막 제조방법Device Separation Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2A도 내지 제2D도는 본 발명의 실시예에 따른 반도체소자의 소자분리막 제조 공정도.2A through 2D are diagrams illustrating a process of fabricating an isolation layer of a semiconductor device in accordance with an embodiment of the present invention.

Claims (1)

반도체기판의 상부에 소자분리영역을 노출하는 제2질화패턴, 열산화막패턴, 제1질화막패턴을 형성하는 단계와, 상기 제2질화막패턴, 열산화패턴, 제1질화막패턴의 측벽에 스페이서를 형성하는 단계와, 상기 제2질화막패턴, 열산화막패턴, 제1질화막패턴 및 스페이서를 식각마스크로 상기 반도체기판을 식각하여 홈을 형성하는 단계와, 상기 홈이 형성된 부위의 반도체기판을 열산화하여 소자분리막을 형성하는 단계와, 상기 제2질화막패턴, 열산화막패턴, 제1질화막패턴 및 스페이서를 제거하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 소자분리막 제조방법.Forming a second nitride pattern, a thermal oxide pattern, and a first nitride pattern to expose the device isolation region on the semiconductor substrate, and forming spacers on sidewalls of the second nitride pattern, the thermal oxidation pattern, and the first nitride pattern Forming a groove by etching the semiconductor substrate using the second nitride film pattern, the thermal oxide film pattern, the first nitride film pattern, and the spacer as an etch mask; and thermally oxidizing the semiconductor substrate at the portion where the groove is formed. Forming a separator; and removing the second nitride layer pattern, the thermal oxide layer pattern, the first nitride layer pattern, and the spacer. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950054960A 1995-12-22 1995-12-22 Device Separation Method of Semiconductor Device KR970053412A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950054960A KR970053412A (en) 1995-12-22 1995-12-22 Device Separation Method of Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950054960A KR970053412A (en) 1995-12-22 1995-12-22 Device Separation Method of Semiconductor Device

Publications (1)

Publication Number Publication Date
KR970053412A true KR970053412A (en) 1997-07-31

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ID=66617621

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950054960A KR970053412A (en) 1995-12-22 1995-12-22 Device Separation Method of Semiconductor Device

Country Status (1)

Country Link
KR (1) KR970053412A (en)

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