KR970053103A - Most transistor manufacturing method - Google Patents

Most transistor manufacturing method Download PDF

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Publication number
KR970053103A
KR970053103A KR1019950050911A KR19950050911A KR970053103A KR 970053103 A KR970053103 A KR 970053103A KR 1019950050911 A KR1019950050911 A KR 1019950050911A KR 19950050911 A KR19950050911 A KR 19950050911A KR 970053103 A KR970053103 A KR 970053103A
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KR
South Korea
Prior art keywords
trench
semiconductor substrate
mos transistor
manufacturing
transistor manufacturing
Prior art date
Application number
KR1019950050911A
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Korean (ko)
Other versions
KR100321754B1 (en
Inventor
나금주
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019950050911A priority Critical patent/KR100321754B1/en
Publication of KR970053103A publication Critical patent/KR970053103A/en
Application granted granted Critical
Publication of KR100321754B1 publication Critical patent/KR100321754B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자의 모스트랜지스터 제조 방법에 있어서; 반도체 기판을 부분식각하여 트렌치를 형성하는 단계; 상기 트렌치에 의해 반도체 기판이 단차진 부위에 게이트 절연막 및 게이트 전도막을 패터닝하는 단계; 노출된 반도체 기판에 소오스/드레인 접합을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 모스트랜지스터 제조 방법에 관한 것으로, 소오스와 드레인 접합이 동일 위상이 아닌 단차를 가지고 형성되도록 함으로써 트랜지스터의 채널 길이를 증대시켜, 좁은 활성영역에서도 단 채널 효과를 극복하는 효과가 있다.The present invention provides a method for manufacturing a MOS transistor of a semiconductor device; Partially etching the semiconductor substrate to form a trench; Patterning a gate insulating film and a gate conductive film on the stepped portion of the semiconductor substrate by the trench; A method of fabricating a MOS transistor, comprising: forming a source / drain junction on an exposed semiconductor substrate. In other words, the short channel effect is overcome even in a narrow active region.

Description

모스트랜지스터의 제조방법Manufacturing method of morph transistor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도 내지 제5도는 본 발명의 일실시예에 따른 모스트랜지스터의 제조 공정도.4 to 5 is a manufacturing process diagram of the MOS transistor according to an embodiment of the present invention.

Claims (3)

반도체 소자의 모스트랜지스터 제조 방법에 있어서; 반도체 기판을 부분식각하여 트렌치를 형성하는 단계; 상기 트렌치에 의해 반도체 기판이 단차진 부위에 게이트 절연막 및 게이트 전도막을 패터닝하는 단계; 노출된 반도체 기판에 소오스/드레인 접합을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 모스트랜지스터 제조 방법.A method of manufacturing a MOS transistor of a semiconductor device; Partially etching the semiconductor substrate to form a trench; Patterning a gate insulating film and a gate conductive film on the stepped portion of the semiconductor substrate by the trench; And forming a source / drain junction on the exposed semiconductor substrate. 제1항에 있어서; 상기 트렌치는 50Å 내지 1500Å의 깊이를 갖도록 형성하는 것을 특징으로 하는 모스트랜지스터 제조 방법.The method of claim 1; The trench is a MOS transistor manufacturing method characterized in that it is formed to have a depth of 50 to 1500Å. 제1항에 있어서; 상기 트렌치는 하부로 갈수록 폭이 좁아지도록 경사식각을 행하여 형성하는 것을 특징으로 하는 모스트랜지스터 제조 방법.The method of claim 1; The trench is a morph transistor manufacturing method characterized in that the inclined etching is formed so that the width becomes narrower toward the bottom. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950050911A 1995-12-16 1995-12-16 Method for fabricating metal oxide semiconductor transistor KR100321754B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950050911A KR100321754B1 (en) 1995-12-16 1995-12-16 Method for fabricating metal oxide semiconductor transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950050911A KR100321754B1 (en) 1995-12-16 1995-12-16 Method for fabricating metal oxide semiconductor transistor

Publications (2)

Publication Number Publication Date
KR970053103A true KR970053103A (en) 1997-07-29
KR100321754B1 KR100321754B1 (en) 2002-05-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950050911A KR100321754B1 (en) 1995-12-16 1995-12-16 Method for fabricating metal oxide semiconductor transistor

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KR (1) KR100321754B1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100602738B1 (en) * 2004-07-29 2006-07-20 주식회사 하이닉스반도체 Memory device and fabricating method for the same
KR100677770B1 (en) * 2005-01-14 2007-02-02 주식회사 하이닉스반도체 Semiconductor device with stack active region and method for manufacturing the same
US7338864B2 (en) 2004-07-27 2008-03-04 Hynix Semiconductor Inc. Memory device and method for fabricating the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618709B1 (en) 2005-03-15 2006-09-06 주식회사 하이닉스반도체 Method for forming gate in semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7338864B2 (en) 2004-07-27 2008-03-04 Hynix Semiconductor Inc. Memory device and method for fabricating the same
DE102004063025B4 (en) * 2004-07-27 2010-07-29 Hynix Semiconductor Inc., Icheon Memory device and method for producing the same
KR100602738B1 (en) * 2004-07-29 2006-07-20 주식회사 하이닉스반도체 Memory device and fabricating method for the same
KR100677770B1 (en) * 2005-01-14 2007-02-02 주식회사 하이닉스반도체 Semiconductor device with stack active region and method for manufacturing the same

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Publication number Publication date
KR100321754B1 (en) 2002-05-13

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