KR970049660A - System bus analyzer of computer system - Google Patents

System bus analyzer of computer system Download PDF

Info

Publication number
KR970049660A
KR970049660A KR1019950069178A KR19950069178A KR970049660A KR 970049660 A KR970049660 A KR 970049660A KR 1019950069178 A KR1019950069178 A KR 1019950069178A KR 19950069178 A KR19950069178 A KR 19950069178A KR 970049660 A KR970049660 A KR 970049660A
Authority
KR
South Korea
Prior art keywords
system bus
trigger condition
search memory
signal
processor
Prior art date
Application number
KR1019950069178A
Other languages
Korean (ko)
Other versions
KR0171768B1 (en
Inventor
윤대준
Original Assignee
유기범
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 유기범, 대우통신 주식회사 filed Critical 유기범
Priority to KR1019950069178A priority Critical patent/KR0171768B1/en
Publication of KR970049660A publication Critical patent/KR970049660A/en
Application granted granted Critical
Publication of KR0171768B1 publication Critical patent/KR0171768B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

본 발명은 컴퓨터 시스템의 시스템 버스 분석장치에 관한 것으로, 제어신호에 따라 시스템 버스의 신호를 저장하기 위한 검색 메모리(26); 트리거 조건을 위한 신호를 출력하고, 상기 검색 메모리의 데이타를 읽어와 가공하여 사용자에게 제공하는 프로세서(21); 상기 프로세서로부터 입력된 돈케어(dont' care) 트리거 조건을 저장하는 마스크 레지스터(22); 상기 프로세서로부터 입력된 케어(care) 트리거 조건을 저장하는 데이타 레지스터(23); 상기 마스크 레지스터 및 데이타 레지스터에 저장된 트리거 조건과 시스템 버스의 신호상태를 버스 클럭마다 비교하는 비교기(24); 및 상기 비교기의 출력에 따라 트리거 조건이 일치되면 시스템 버스의 신호상태를 검색 메모리에 저장하도록 검색 메모리 어드레스 및 라이트신호를 출력하는 검색 메모리 저장 제어신호 생성부(25)를 포함하여 구성되어 시스템 버스 클럭 단위로 트리거 조건을 입력받아 시스템 버스의 상태를 검색하므로써 고속 중형 컴퓨터의 시스템 상태를 효율적으로 시험하거나 컴퓨터의 성능을 분석할 수 있는 효과가 있다.The present invention relates to a system bus analyzer of a computer system, comprising: a search memory (26) for storing a signal of a system bus in accordance with a control signal; A processor 21 for outputting a signal for a trigger condition, reading and processing data of the search memory and providing the same to a user; A mask register 22 for storing a don 'care trigger condition input from the processor; A data register (23) for storing a care trigger condition input from the processor; A comparator (24) for comparing a signal condition of a system bus with a trigger condition stored in the mask register and the data register for each bus clock; And a search memory storage control signal generator 25 outputting a search memory address and a write signal to store the signal state of the system bus in the search memory when a trigger condition is matched according to the output of the comparator. By retrieving the state of the system bus by receiving the trigger condition in units, it is possible to efficiently test the system state of a high-speed medium-size computer or to analyze the performance of the computer.

Description

컴퓨터 시스템의 시스템 버스 분석장치System bus analyzer of computer system

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 시스템 버스 분석장치를 도시한 블럭도.2 is a block diagram showing a system bus analyzer according to the present invention.

제3도는 본 발명이 적용되는 버스 정보 분석기를 도시한 블럭도.3 is a block diagram showing a bus information analyzer to which the present invention is applied.

Claims (1)

다중 프로세서 시스템의 시스템 버스상의 신호들을 버스 클럭 단위로 검색하여 모니터하도록 된 시스템 버스 분석기에 있어서, 제어신호에 따라 시스템 버스의 신호를 저장하기 위한 검색 메모리(26); 트리거 조건을 위한 신호를 출력하고, 검색 메모리의 데이타를 읽어와 가공하여 사용자에게 제공하는 프로세서(21); 상기 프로세서로부터 입력된 돈케어 트리거 조건을 저장하는 마스크 레지스터(22); 상기 프로세서로부터 입력된 케어 트리거 조건을 저장하는 데이타 레지스터(23);상기 마스크 레지스터 및 데이타 레지스터에 저장된 트리거 조건과 시스템 버스의 신호정보를 버스 클럭마다 비교하는 비교기(24); 및 상기 비교기의 출력에 따라 트리거 조건이 일치되면 소정의 방식으로 시스템 버스의 신호상태를 검색 메모리에 저장하도록 상기 검색 메모리의 저장하도록 검색 메모리의 어드레스 및 라이트신호를 출력하는 검색 메모리 저장 제어신호 생성부(25)로 구성되는 컴퓨터 시스템의 시스템 버스 분석장치.A system bus analyzer configured to retrieve and monitor signals on a system bus of a multiprocessor system by a bus clock unit, the system bus analyzer comprising: a search memory 26 for storing signals of a system bus according to a control signal; A processor 21 for outputting a signal for a trigger condition, reading and processing data in a search memory and providing the same to a user; A mask register (22) for storing the money care trigger condition input from the processor; A data register (23) for storing a care trigger condition input from the processor; a comparator (24) for comparing the trigger condition stored in the mask register and the data register with signal information of a system bus for each bus clock; And a search memory storage control signal generation unit configured to output an address and a write signal of a search memory to store the search memory to store the signal state of a system bus in the search memory in a predetermined manner when a trigger condition is matched according to the output of the comparator. A system bus analyzer for a computer system, which is composed of (25). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069178A 1995-12-30 1995-12-30 System bus analysis apparatus of computer system KR0171768B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069178A KR0171768B1 (en) 1995-12-30 1995-12-30 System bus analysis apparatus of computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069178A KR0171768B1 (en) 1995-12-30 1995-12-30 System bus analysis apparatus of computer system

Publications (2)

Publication Number Publication Date
KR970049660A true KR970049660A (en) 1997-07-29
KR0171768B1 KR0171768B1 (en) 1999-03-30

Family

ID=19448329

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950069178A KR0171768B1 (en) 1995-12-30 1995-12-30 System bus analysis apparatus of computer system

Country Status (1)

Country Link
KR (1) KR0171768B1 (en)

Also Published As

Publication number Publication date
KR0171768B1 (en) 1999-03-30

Similar Documents

Publication Publication Date Title
US4375678A (en) Redundant memory arrangement providing simultaneous access
KR930022210A (en) Cache miss buffer
KR840001368A (en) Selective Cache Clearing Method and Device in Data Processing System
KR970012203A (en) Data processing system for executing trace functions and their methods
KR940024591A (en) Computer devices
KR950034265A (en) Associative memory
KR0159533B1 (en) Method and apparatus for non-atomic level parity protection for storage of data in random access memory
SE9500289D0 (en) data transmission system
KR970049537A (en) CPI to prevent program malfunction
GB2244158A (en) Cache memory with write buffer
KR920004946A (en) VGA input / output port access circuit
KR880011676A (en) Block access method using cache memory
KR970049660A (en) System bus analyzer of computer system
KR970049661A (en) System bus analyzer of computer system
KR970049659A (en) System bus analyzer of computer system
KR940007689A (en) Data processor
KR940022305A (en) Translation device
KR910001545A (en) CPU core
KR970002413B1 (en) Trace memory module in the bus information processing unit
KR100211076B1 (en) Address space extension apparatus
KR960002006A (en) Cache Memory Filtering Device of Multiprocessor
KR920009453B1 (en) Bus situation analyzer
KR920013162A (en) Bus Status Analyzer of Multiprocessor
RU2065207C1 (en) Associative memory matrix
KR920000069A (en) Memory IC with Parallel and Serial Output Conversion

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee