KR970030534A - Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body - Google Patents
Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body Download PDFInfo
- Publication number
- KR970030534A KR970030534A KR1019950041032A KR19950041032A KR970030534A KR 970030534 A KR970030534 A KR 970030534A KR 1019950041032 A KR1019950041032 A KR 1019950041032A KR 19950041032 A KR19950041032 A KR 19950041032A KR 970030534 A KR970030534 A KR 970030534A
- Authority
- KR
- South Korea
- Prior art keywords
- package body
- semiconductor chip
- package
- hole
- pattern
- Prior art date
Links
Landscapes
- Wire Bonding (AREA)
Abstract
본 발명은 상부와 하부에 각각 적어도 하나 이상의 캐비티를 갖고 있고 상기 상부와 하부의 캐비티를 연결하는 관통구멍을 갖고 있으며 상기 패키지 몸체의 상부의 캐비티에 노출된 부위를 갖고 있는 복수개의 패턴리드가 형성되어 있고 도전성 패턴이 상기 패턴리드와 전기적으로 연결된 패키지 몸체를 준비하는 단계와, 상기 패키지 몸체의 외측면에 상기 도전성 패턴과 전기적으로 연결되도록 외부 접속 단자를 부착하는 단계와, 일면의 중앙부에 복수개의 본딩패드가 형성된 반도체 칩을 상기 본딩패드가 상기 관통구멍에 노출되도록 함과 동시에 상기 반도체 칩이 상기 패키지 몸체의 하부의 캐비티에 위치하도록 소정의 접착수단으로 상기 패키지 몸체에 부착하는 단계와, 상기 본딩패드가 대응되는 상기 패턴리드와 전기적으로 연결하는 단계를 포함하는 것을 특징으로 하는 패키지 몸체의 관통구멍에 노출된 본딩패드에 와이어 본딩된 반도체 칩 패키지 제조 방법을 제공함으로써, 패키지 크기를 축소하고 신뢰성 높은 와이어 본딩상태를 제공하는 효과를 나타낸다.According to the present invention, a plurality of pattern leads are formed, each having at least one cavity at an upper portion and a lower portion, a through hole connecting the upper and lower cavities, and having a portion exposed to the upper cavity of the package body. Preparing a package body having a conductive pattern electrically connected to the pattern lead, attaching an external connection terminal to an outer surface of the package body to be electrically connected to the conductive pattern, and bonding a plurality of bondings to a central portion of one surface of the package body; Attaching the pad on which the semiconductor chip is formed to be exposed to the through hole and simultaneously placing the semiconductor chip on the package body with a predetermined bonding means so that the semiconductor chip is located in a cavity below the package body; Electrically connecting the pattern lead to By providing a method of manufacturing a semiconductor chip package wire bonded to the bonding pad exposed to the through-holes of the package body, it has an effect of reducing the package size and providing a reliable wire bonding state.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제2a도는 본 발명에 따른 반도체 칩 패키지의 제1실시예를 나타낸 단면도.2A is a cross-sectional view showing a first embodiment of a semiconductor chip package according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950041032A KR970030534A (en) | 1995-11-13 | 1995-11-13 | Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950041032A KR970030534A (en) | 1995-11-13 | 1995-11-13 | Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970030534A true KR970030534A (en) | 1997-06-26 |
Family
ID=66586873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950041032A KR970030534A (en) | 1995-11-13 | 1995-11-13 | Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970030534A (en) |
-
1995
- 1995-11-13 KR KR1019950041032A patent/KR970030534A/en not_active Application Discontinuation
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5615089A (en) | BGA semiconductor device including a plurality of semiconductor chips located on upper and lower surfaces of a first substrate | |
KR920010853A (en) | Resin-sealed semiconductor device | |
JP2000133767A (en) | Laminated semiconductor package and its manufacture | |
KR960026505A (en) | Semiconductor device and manufacturing method thereof | |
KR970013236A (en) | Chip Scale Package with Metal Circuit Board | |
KR950030323A (en) | Semiconductor device and production method of semiconductor device and semiconductor module | |
MY119797A (en) | Resin-molded semiconductor device having a lead on chip structure | |
KR970030534A (en) | Manufacturing method of semiconductor chip package wire bonded to bonding pad exposed to through hole of package body | |
KR910017598A (en) | Mounting Structure of Semiconductor Device | |
KR200211272Y1 (en) | Chip size package | |
KR0163524B1 (en) | Ball grid array package formed conducting pattern on the inner face of cap type package body | |
KR970018441A (en) | Ball Grid Array Package with Lead-on Chip Technology | |
KR200169730Y1 (en) | Lead frame for semiconductor package | |
KR970053649A (en) | Wireless Semiconductor Package | |
KR970030689A (en) | Ceramic package with center pad type semiconductor chip | |
KR0167281B1 (en) | Blp package | |
KR100402107B1 (en) | Wire bonding method of sop | |
JPH07106462A (en) | Semiconductor device | |
JP2005135938A (en) | Semiconductor device and its manufacturing method | |
KR980006210A (en) | Board for Multichip Package with Added Test Pad | |
KR970003183Y1 (en) | Structure of wire bonding on the semiconductor package | |
KR970024059A (en) | Manufacturing method of lead-on-chip package and rod-on-chip package using metal bumper | |
KR970030745A (en) | Manufacturing method of multi-chip package with solder pre-plating lead frame | |
KR970024081A (en) | Chip scale package with leadframe | |
KR940008052A (en) | Semiconductor package |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |