KR970029746A - Dual Back Bias Supply - Google Patents

Dual Back Bias Supply Download PDF

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Publication number
KR970029746A
KR970029746A KR1019950040480A KR19950040480A KR970029746A KR 970029746 A KR970029746 A KR 970029746A KR 1019950040480 A KR1019950040480 A KR 1019950040480A KR 19950040480 A KR19950040480 A KR 19950040480A KR 970029746 A KR970029746 A KR 970029746A
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KR
South Korea
Prior art keywords
back bias
bias voltage
substrate
semiconductor memory
level
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KR1019950040480A
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Korean (ko)
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KR100211759B1 (en
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최명찬
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김광호
삼성전자 주식회사
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Priority to KR1019950040480A priority Critical patent/KR100211759B1/en
Publication of KR970029746A publication Critical patent/KR970029746A/en
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Publication of KR100211759B1 publication Critical patent/KR100211759B1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

동일한 반도체칩의 기판상에 형성되는 엔모오스 트랜지스터 및 상기 엔모오스 트랜지스터들로 구성된 로직회로들의 동작 특성을 고려하여 백바이어스전압을 다르게 공급할 수 있도록 서로다른 영역에 서로다른 레벨의 백바이어스를 공급하는 장치에 관한 것이다. 상기의 듀얼 백바이어스전압 발생기는 동일 반도체 기판상에 형성되어 소정 레벨의 백바이어스전압을 입력받는 제1 및 제2기판영역과, 전원전압의 입력에 응답하여 제1레벨의 백바이어스전압을 발생하여 상기 제1기판영역에 공급하는 백바이어스전압 발생수단과, 상기 백바이어스전압 발생수단의 출력노드와 상기 제2기판영역 사이에 접속되어 상기 발생된 제1레벨의 백바이어스전압을 제2레벨의 백바이어스전압으로 변환하여 출력하는 전압레벨변환수단을 포함하여 구성된다.Apparatus for supplying different levels of back bias to different regions so as to supply back bias voltage differently in consideration of the operating characteristics of the NMOS transistor formed on the substrate of the same semiconductor chip and the logic circuits formed of the ENMOS transistors It is about. The dual back bias voltage generator is formed on the same semiconductor substrate to generate first and second substrate regions to receive a predetermined level of back bias voltage, and generates a back bias voltage of a first level in response to input of a power supply voltage. The back bias voltage generating means for supplying the first substrate region and the output node of the back bias voltage generating means and the second substrate region are connected to the back bias voltage of the first level. And voltage level converting means for converting and outputting the bias voltage.

Description

듀얼 백 바이어스 공급 장치Dual Back Bias Supply

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따른 듀얼 백바이어스 공급을 서로 다른 영역에 각각 공급하기 위한 반도체 기판상의 구성관계를 도시한 도면.1 is a diagram showing a configuration relationship on a semiconductor substrate for supplying dual back bias supplies to different regions, respectively, according to the present invention.

제2도는 본 발명에 따른 듀얼 백바이어스를 서로다른 영역의 웰이 공급시의 아이솔레이션의 관계를 도시한 도면.2 is a diagram showing the relationship between the isolation of the dual back bias according to the present invention when wells of different regions are supplied.

Claims (8)

반도체 메모리의 듀얼 백 바이어스 공급 장치에 있어서, 동일 반도체 기판상에 형성되어 소정 레벨의 백바이어스전압을 입력받는 제1 및 제2기판영역과, 전원전압의 입력에 응답하여 제1레벨의 백바이어스전압을 발생하여 상기 제1기판영역에 공급하는 백바이어스전압 발생수단과, 상기 백바이어스전압 발생수단의 출력노드와 상기 제2기판영역 사이에 접속되어 상기 발생된 제1레벨의 백바이어스전압을 제2레벨의 백바이어스전압으로 변환하여 출력하는 전압레벨변환수단을 포함함을 특징으로 하는 반도체 메모리 장치.A dual back bias supply apparatus for a semiconductor memory, comprising: first and second substrate regions formed on the same semiconductor substrate and receiving a back bias voltage of a predetermined level, and a back bias voltage of a first level in response to input of a power supply voltage; A back bias voltage generating means for generating a second bias supply to the first substrate region, and an output node of the back bias voltage generating means and the second substrate region to generate a second And a voltage level converting means for converting and outputting the back bias voltage at a level. 제1항에 있어서, 상기 제1기판영역과 제2기판영역들 각각은 상기 반도체 기판과 다른 불순물로 확산된 웰에 의해 전기적으로 분리됨을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device as claimed in claim 1, wherein each of the first substrate region and the second substrate region is electrically separated by a well diffused with impurities different from the semiconductor substrate. 제1항 또는 제2항에 있어서, 상기 전압레벨변환수단은 다이오드 접속된 모오스트랜지스터임을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device according to claim 1 or 2, wherein the voltage level converting means is a diode-connected MOS transistor. 제3항에 있어서, 상기 다이오드는 엔모오스 트랜지스터임을 특징으로 하는 반도체 메모리 장치.4. The semiconductor memory device of claim 3, wherein the diode is an enMOS transistor. 제3항에 있어서, 상기 다이오드는 피모오스 트랜지스터임을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 3, wherein the diode is a PMOS transistor. 제4항에 있어서, 상기 엔모오스 트랜지스터는, 엔형 반도체 기판상에서 서로 이격되어 형성된 제1, 제2피형 웰들과, 상기 제1, 제2피형 웰들의 각각에 형성되어진 제1, 제2엔형 영역에 접속된 소오스, 드레인 전극 및 상기 제1, 제2피형 웰들을 접속하는 게이트전극을 구비하여 구성되며, 상기 게이트 전극과 상기 드레인전극이 접속됨을 특징으로 하는 반도체 메모리 장치.The NMOS transistor of claim 4, wherein the NMOS transistor comprises first and second wells formed on the N-type semiconductor substrate and spaced apart from each other, and the first and second N-type regions formed in each of the first and second wells. And a gate electrode for connecting the connected source and drain electrodes and the first and second wells, wherein the gate electrode and the drain electrode are connected to each other. 반도체 메모리의 듀얼 백 바이어스 공급 장치에 있어서, 동일한 반도체 기판상에 형성되어 소정 레벨의 백바이어스전압을 입력받는 제1 및 제2기판영역과, 각각의 출력노드가 상기 제1 및 제2기판영역에 각각 접속되어 있으며, 전원전압의 입력에 응답하여 서로다른 레벨의 백바이어스전압을 발생하는 제1 및 제2백바이스전압 발생수단으로 구성함을 특징으로 하는 반도체 메모리 장치.A dual back bias supply apparatus for a semiconductor memory, comprising: first and second substrate regions formed on the same semiconductor substrate and receiving a back bias voltage of a predetermined level, and respective output nodes are provided in the first and second substrate regions; And first and second back bias voltage generating means connected to each other and generating back bias voltages having different levels in response to input of a power supply voltage. 제7항에 있어서, 상기 제1기판영역과 제2기판영역들 각각은 상기 반도체 기판과 다른 불순불로 확산된 웰에 의해 전기적으로 분리됨을 특징으로 하는 반도체 메모리 장치.10. The semiconductor memory device of claim 7, wherein each of the first substrate region and the second substrate region is electrically separated by a well diffused impurity different from the semiconductor substrate. ※ 참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950040480A 1995-11-09 1995-11-09 Dual back bias voltage supplying device KR100211759B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950040480A KR100211759B1 (en) 1995-11-09 1995-11-09 Dual back bias voltage supplying device

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Application Number Priority Date Filing Date Title
KR1019950040480A KR100211759B1 (en) 1995-11-09 1995-11-09 Dual back bias voltage supplying device

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KR970029746A true KR970029746A (en) 1997-06-26
KR100211759B1 KR100211759B1 (en) 1999-08-02

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624508B1 (en) * 2005-03-17 2006-09-19 고려대학교 산학협력단 Circuit for generation negative substrate voltage
KR100679255B1 (en) * 2004-09-02 2007-02-06 삼성전자주식회사 Semiconductor memory device
KR100762880B1 (en) * 2006-03-24 2007-10-08 주식회사 하이닉스반도체 Semiconductor memory device including back bias generation circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100679255B1 (en) * 2004-09-02 2007-02-06 삼성전자주식회사 Semiconductor memory device
KR100624508B1 (en) * 2005-03-17 2006-09-19 고려대학교 산학협력단 Circuit for generation negative substrate voltage
KR100762880B1 (en) * 2006-03-24 2007-10-08 주식회사 하이닉스반도체 Semiconductor memory device including back bias generation circuit

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