KR970017690A - Semiconductor memory device with burn-in short circuit to prevent overcurrent - Google Patents

Semiconductor memory device with burn-in short circuit to prevent overcurrent Download PDF

Info

Publication number
KR970017690A
KR970017690A KR1019950030735A KR19950030735A KR970017690A KR 970017690 A KR970017690 A KR 970017690A KR 1019950030735 A KR1019950030735 A KR 1019950030735A KR 19950030735 A KR19950030735 A KR 19950030735A KR 970017690 A KR970017690 A KR 970017690A
Authority
KR
South Korea
Prior art keywords
signal
cells
burn
applying
semiconductor memory
Prior art date
Application number
KR1019950030735A
Other languages
Korean (ko)
Other versions
KR0172399B1 (en
Inventor
박희철
권국환
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950030735A priority Critical patent/KR0172399B1/en
Priority to US08/715,549 priority patent/US5732032A/en
Priority to JP8248308A priority patent/JPH09120697A/en
Publication of KR970017690A publication Critical patent/KR970017690A/en
Application granted granted Critical
Publication of KR0172399B1 publication Critical patent/KR0172399B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

1. 청구범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION

반도체 메모리 장치의 번-인 테스트에 관한 것이다.A burn-in test of a semiconductor memory device.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

번-인 단축회로를 사용할시 발생될 수 있는 과전류를 방지할 수 있는 반도체 메모리 장치를 제공함에 있다.It is an object of the present invention to provide a semiconductor memory device capable of preventing overcurrent that may occur when using a burn-in short circuit.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

셀들의 결합상태를 판별하기 위한 테스트신호를 프리차아지부내의 트랜지스터들에 인가하고, 이어 상기 셀들을 선택하기 위한 선택신호를 소정의 간격을 두고 상기 셀들에 인가하는 제1과정과, 반전된 상기 선택신호들을 상기 셀들에 인가하고, 이어 반전된 상기 테스트신호를 소정의 간격을 두고 상기 트랜지스터들에 인가하여 턴-온시키는 제2과정을 구비한다.The first step of applying a test signal for determining the coupling state of the cells to the transistors in the precharge section, and then applying a selection signal for selecting the cells to the cells at predetermined intervals, and the inverted selection And applying a signal to the cells, and then applying the inverted test signal to the transistors at predetermined intervals to turn on the signals.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 메모리 장치에 적합하게 사용된다.It is suitably used for semiconductor memory devices.

Description

과전류를 방지하기 위한 번-인 단축회로를 내장한 반도체 메모리 장치Semiconductor memory device with burn-in short circuit to prevent overcurrent

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따라 메모리 셀들의 결합상태를 테스트하기 위한 개략적인 회로도.3 is a schematic circuit diagram for testing a coupling state of memory cells in accordance with the present invention.

Claims (6)

데이타가 저장된 복수개의 셀들과, 상기 셀들의 좌우측에 접속된 비트라인쌍들과, 상기 셀들의 상하측에 접속된 다수개의 워드라인들과, 상기 비트라인쌍들의 일측에 접속된 트랜지스터들로 구성된 프라차아지부와, 상기 프리차아지부에 상기 셀들을 테스트하기 위한 테스트신호를 인가하기 위한 번-인 제어회로와, 상기 비트 라인쌍들과 상기 워드라인들에 각기 접속되어 상기 셀들을 선택하기 위한 선택신호를 인가하는 디코더부를 적어도 구비하는 반도체 메모리 장치의 번-인 테스트방법에 있어서, 상기 테스트신호를 인가하여 트랜지스터들을 오프상태로 만들고, 이어 상기 선택신호를 소정의 간격을 두고 상기 셀들에 인가하는 제1과정과, 반전된 상기 선택신호들을 상기 셀들에 인가하고, 이어 반전된 상기 테스트신호를 소정의 간격을 두고 트랜지스터들에 인가하여 턴-온시키는 제2과정이 반복적으로 실행됨을 특징으로 하는 번-인 테스트방법.It consists of a plurality of cells in which data is stored, bit line pairs connected to the left and right sides of the cells, a plurality of word lines connected to the upper and lower sides of the cells, and transistors connected to one side of the bit line pairs. A burn-in control circuit for applying a test signal for testing the cells to the charge unit, the precharge unit, and a selection signal connected to the bit line pairs and the word lines to select the cells, respectively. A burn-in test method of a semiconductor memory device including at least a decoder unit for applying a first circuit, the method comprising: applying a test signal to turn off transistors, and then applying the selection signal to the cells at a predetermined interval. And applying the inverted selection signals to the cells, and then inverting the test signals at predetermined intervals. Applied to register and turn-times that of the second iterative process that runs on a feature-test method. 제1항에 있어서, 상기 테스트신호는 상기 선택신호와 상보적인 신호임을 특징으로 하는 번-인 테스트방법.The burn-in test method of claim 1, wherein the test signal is a signal complementary to the selection signal. 데이타가 저장된 복수개의 셀들과, 상기 셀들의 좌우측에 접속된 비트라인쌍들과, 상기 셀들의 상하측에 접속된 다수개의 워드라인들과, 상기 비트라인쌍들의 일측에 접속된 트랜지스터들로 구성된 프라차아지부와, 상기 프리차아지부에 상기 셀들을 테스트하기 위한 테스트신호를 인가하기 위한 번-인 제어회로와, 상기 비트 라인쌍들과 상기 워드라인들에 각기 접속되어 상기 셀들을 선택하기 위한 선택신호를 인가하는 디코더부를 적어도 구비하는 반도체 메모리 장치에 있어서 상기 번-인 제어회로와 상기 프리차아지부 사이에 접속되고, 상기 번-인 제어회로의 출력신호에 응답하여 상기 테스트신호를 발생하는 제1제어부와; 상기 번-인 제어회로와 상기 디코더부사이에 접속되고, 상기 출력신호에 응답하여 상기 선택신호를 제어하기 위한 제어신호를 발생 하는 제2제어부를 구비함을 특징으로 하는 반도체 메모리 장치.It consists of a plurality of cells in which data is stored, bit line pairs connected to the left and right sides of the cells, a plurality of word lines connected to the upper and lower sides of the cells, and transistors connected to one side of the bit line pairs. A burn-in control circuit for applying a test signal for testing the cells to the charge unit, the precharge unit, and a selection signal connected to the bit line pairs and the word lines to select the cells, respectively. 12. A semiconductor memory device comprising at least a decoder section for applying a first control section, said first control section being connected between said burn-in control circuit and said precharge section and generating said test signal in response to an output signal of said burn-in control circuit. Wow; And a second control unit connected between the burn-in control circuit and the decoder unit, the second control unit generating a control signal for controlling the selection signal in response to the output signal. 제3항에 있어서, 상기 테스트신호는 상기 제어신호와 상보적인 신호임을 특징으로 하는 반도체 메모리 장치.The semiconductor memory device of claim 3, wherein the test signal is a signal complementary to the control signal. 제4항에 있어서, 상기 제1제어부는 인버어터를 통해 반전된 상기 출력신호를 입력으로 하는 제1입력단자와 상기 반전된 출력신호를 제1지연회로를 통해 지연시킨 신호를 입력으로 하는 제2입력단자를 가지는 제1낸드 게이트를 가짐을 특징으로 하는 반도체 메모리 장치.The second control unit of claim 4, wherein the first controller is configured to input a first input terminal for inputting the inverted output signal through an inverter and a signal for delaying the inverted output signal through a first delay circuit. And a first NAND gate having an input terminal. 제5항에 있어서, 상기 제2제어부는 상기 출려신호를 입력으로 하는 제1입력단자와 상기 출력신호를 제2지연회로를 통해 지연시킴 신호를 입력으로 하는 제2입력단자를 가지는 제2낸드게이트를 가짐을 특징으로 하는 반도체 메모리 장치.6. The second NAND gate of claim 5, wherein the second control unit has a first input terminal for inputting the output signal and a second input terminal for inputting a delay signal of the output signal through a second delay circuit. Semiconductor memory device characterized in that it has a. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950030735A 1995-09-19 1995-09-19 Semiconductor memory device having burn-in shortening circuit for preventing over-current KR0172399B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019950030735A KR0172399B1 (en) 1995-09-19 1995-09-19 Semiconductor memory device having burn-in shortening circuit for preventing over-current
US08/715,549 US5732032A (en) 1995-09-19 1996-09-19 Semiconductor memory device having a burn-in control circuit and burn-in test method thereof
JP8248308A JPH09120697A (en) 1995-09-19 1996-09-19 Burn-in test method for semiconductor memory device and control circuit for burn-in timing for it

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950030735A KR0172399B1 (en) 1995-09-19 1995-09-19 Semiconductor memory device having burn-in shortening circuit for preventing over-current

Publications (2)

Publication Number Publication Date
KR970017690A true KR970017690A (en) 1997-04-30
KR0172399B1 KR0172399B1 (en) 1999-03-30

Family

ID=19427234

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950030735A KR0172399B1 (en) 1995-09-19 1995-09-19 Semiconductor memory device having burn-in shortening circuit for preventing over-current

Country Status (3)

Country Link
US (1) US5732032A (en)
JP (1) JPH09120697A (en)
KR (1) KR0172399B1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10199295A (en) * 1997-01-10 1998-07-31 Fujitsu Ltd Semiconductor integrated circuit
KR100240883B1 (en) * 1997-02-06 2000-01-15 윤종용 Cmos sram device
KR100234377B1 (en) * 1997-04-10 1999-12-15 윤종용 Redundancy memory cell control circuit and method for memory device
KR100268434B1 (en) * 1997-12-29 2000-10-16 윤종용 Semiconductor memory device and burn-in test method thereof
US6603338B1 (en) 1998-10-30 2003-08-05 Stmicroelectronics, Inc. Device and method for address input buffering
US6294939B1 (en) * 1998-10-30 2001-09-25 Stmicroelectronics, Inc. Device and method for data input buffering
US6400171B2 (en) * 1999-03-22 2002-06-04 International Business Machines Corp. Method and system for processing integrated circuits
KR100370173B1 (en) * 2001-04-11 2003-01-30 주식회사 하이닉스반도체 Integrated circuit of semiconductor device
US7275188B1 (en) 2003-10-10 2007-09-25 Integrated Device Technology, Inc. Method and apparatus for burn-in of semiconductor devices
US7859925B1 (en) * 2006-03-31 2010-12-28 Cypress Semiconductor Corporation Anti-fuse latch self-test circuit and method
US7821859B1 (en) 2006-10-24 2010-10-26 Cypress Semiconductor Corporation Adaptive current sense amplifier with direct array access capability
US8766680B2 (en) 2012-09-26 2014-07-01 Freescale Semiconductor, Inc. Voltage translation circuit
US9209819B2 (en) 2012-09-26 2015-12-08 Freescale Semiconductor, Inc. Phase locked loop with burn-in mode
US8558591B1 (en) 2012-09-28 2013-10-15 Freescale Semiconductor, Inc. Phase locked loop with power supply control

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960005387Y1 (en) * 1992-09-24 1996-06-28 문정환 Burn-in test apparatus of semiconductor memory
KR970010658B1 (en) * 1993-11-26 1997-06-30 삼성전자 주식회사 Semiconductor device and burn-in method
US5440524A (en) * 1994-02-01 1995-08-08 Integrated Device Technology, Inc. Method and apparatus for simuilataneous long writes of multiple cells of a row in a static ram

Also Published As

Publication number Publication date
KR0172399B1 (en) 1999-03-30
JPH09120697A (en) 1997-05-06
US5732032A (en) 1998-03-24

Similar Documents

Publication Publication Date Title
KR870008439A (en) Time delay circuit of semiconductor device
KR950006874A (en) Semiconductor Nonvolatile Memory
KR970017690A (en) Semiconductor memory device with burn-in short circuit to prevent overcurrent
KR900017273A (en) Semiconductor memory
KR920013449A (en) Read / Write Memory with Improved Write Driver
KR920013450A (en) Semiconductor memory with time-out control for read and write operations
KR940002865A (en) Burn-in enable circuit and burn-in test method of semiconductor memory device
KR950025952A (en) Semiconductor integrated circuit device
KR970017616A (en) Semiconductor memory device with data output path for high speed access
KR980004989A (en) Apparatus and method for data sensing of multi-bit memory cells
KR880008334A (en) How to detect data at high speed and its dynamic semiconductor memory
US5909402A (en) Circuit for driving/controlling sensing amplifier
KR960025777A (en) Semiconductor Memory Device With Precharge Circuit
KR970030584A (en) Semiconductor memory
KR970017658A (en) Semiconductor memory device to reduce cycle time
KR950015394A (en) Static random access memory
KR930024015A (en) Bit line sensing control circuit
KR100253354B1 (en) Operation testing apparatus for semiconductor memory
KR930022384A (en) Semiconductor memory
KR920022300A (en) Semiconductor memory device with improved write operation
KR960039000A (en) A semiconductor static memory device having a pulse generator for reducing write cycle time
KR970049568A (en) Memory device for sequential access
KR0167690B1 (en) Semiconductor memory apparatus removing address disturbance
KR950015778A (en) Multi-bit Test Circuit of Semiconductor Memory Device
KR900015141A (en) Semiconductor memory device

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20110930

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee