KR970008505A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- KR970008505A KR970008505A KR1019950019950A KR19950019950A KR970008505A KR 970008505 A KR970008505 A KR 970008505A KR 1019950019950 A KR1019950019950 A KR 1019950019950A KR 19950019950 A KR19950019950 A KR 19950019950A KR 970008505 A KR970008505 A KR 970008505A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor chip
- die pad
- leads
- back surface
- insulating polymer
- Prior art date
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
패키지 몸체에 하부면에 반도체 칩이나 다이패드등이 노출되어 있는 UTSOP형 반도체 패키지에서 외부리이드들이 패키지 몸체의 하부로 ㄷ자 형상으로 절곡되어 있으며, 상기 외부리이드들의 단부와 상기 노출된 반도체 칩이나 다이패드의 사이에 절연성 폴리머층을 개재시켜 상기 외부리이드들의 단부를 절연성 폴리머층과 접착시켜 반도체 패키지를 형성하였으므로, 외부리이드가 차지하는 실장면적이 감소되어 고밀도실장에 유리하고, 절연성 폴리머층에 의해 납땜 리플로우 공정시의 외부리이드와 반도체 칩이나 다이패드간의 단락을 방지하므로 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 잇점이 있다.In the UTSOP-type semiconductor package in which a semiconductor chip or a die pad is exposed on the bottom surface of the package body, external leads are bent in a U shape at the bottom of the package body, and ends of the external leads and the exposed semiconductor chip or die pad are exposed. Since the semiconductor package is formed by bonding the ends of the outer leads with the insulating polymer layer through the insulating polymer layer, the mounting area occupied by the outer leads is reduced, which is advantageous for high density mounting, and the solder reflow is performed by the insulating polymer layer. Since the short circuit between the external lead during the process and the semiconductor chip or the die pad is prevented, there is an advantage that the process yield and the reliability of device operation can be improved.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제3도(A)는 본 발명의 일실시예에 따른 반도체 패키지의 단면도.3A is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
Claims (4)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950019950A KR970008505A (en) | 1995-07-07 | 1995-07-07 | Semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950019950A KR970008505A (en) | 1995-07-07 | 1995-07-07 | Semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
KR970008505A true KR970008505A (en) | 1997-02-24 |
Family
ID=66526288
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950019950A KR970008505A (en) | 1995-07-07 | 1995-07-07 | Semiconductor package |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970008505A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100726778B1 (en) * | 2006-01-11 | 2007-06-11 | 삼성테크윈 주식회사 | Lead frame for semiconductor package and method of manufacturing the semiconductor package |
-
1995
- 1995-07-07 KR KR1019950019950A patent/KR970008505A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100726778B1 (en) * | 2006-01-11 | 2007-06-11 | 삼성테크윈 주식회사 | Lead frame for semiconductor package and method of manufacturing the semiconductor package |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E601 | Decision to refuse application |