KR970004510A - Mounted bit error rate measuring circuit and its control method - Google Patents
Mounted bit error rate measuring circuit and its control method Download PDFInfo
- Publication number
- KR970004510A KR970004510A KR1019950018992A KR19950018992A KR970004510A KR 970004510 A KR970004510 A KR 970004510A KR 1019950018992 A KR1019950018992 A KR 1019950018992A KR 19950018992 A KR19950018992 A KR 19950018992A KR 970004510 A KR970004510 A KR 970004510A
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- South Korea
- Prior art keywords
- test pattern
- error rate
- bit error
- counting
- data
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- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
1. 청구 범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
디지탈 통신시스템의 비트에러율 측정회로 및 방법에 관련된 기술.A technique related to a bit error rate measuring circuit and method of a digital communication system.
2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention
종래에는 비트에러율을 측정하기 위해 별도의 측정장비가 필요하였고, 온-디멘드로 피시험장비의 비트에러율 테스트하는 것이 불가능하였으며, 장비를 야전 운용할 경우 여러가지 환경과 조건하에서 테스트를 하기에는 많은 어려움이 있었으므로 이를 개선하기 위함.Conventionally, a separate measuring device was required to measure the bit error rate, and it was impossible to test the bit error rate of the equipment under test by on-demand, and when the equipment was field-operated, it was difficult to test under various environments and conditions. So to improve this.
3. 발명의 해결방법의 요지3. Summary of Solution to Invention
본 비트에러율 측정회로는, 송신측과 수신측을 가지고 순환 반복 코드워드 시그날링에 의한 통신을 수행하는 시스템에 있어서, 정상모드와 테스트모드 중 어느 하나의 패스를 선택하기 위한 모드선택부와, 테스트모드 하에서 소정 횟수 이상 반복적으로 수신되는 동기 데이타로부터 테스트패턴을 검출하기 위한 테스트패턴 검출부와, 상기 테스트패턴의 검출완료시에 동작을 개시하며, 상기 동기 데이타와 상기 테스트패턴을 비교하여 비교신호를 발생하고, 매회 비교시마다 소정의 펄스신호를 발생하기 위한 테스트패턴 비교부와, 상기 테스트패턴의 검출완료시에 동작을 개시하며, 상기 펄스신호를 카운트하여 수신되는 데이타와 비트수를 카운트하기 위한 수신데이타 카운트부와, 상기 테스트패턴 비교부에서 출력되는 비교신호를 수신하여 에러가 발생한 비트수를 카운트하기 위한 에러 카운트부와, 상기 수신데이타 카운트부에서 출력하는 비트단위의 수신데이타의 수와 상기 에러 카운트부에서 출력된 에러의 수로써 비트에러율을 연산하기 위한 비트에러율 연산부로 구성되어 상기 수신측에 실장된다.The bit error rate measuring circuit includes a mode selection unit for selecting one of a normal mode and a test mode in a system for performing communication by cyclic repetitive codeword signaling between a transmitting side and a receiving side. A test pattern detection unit for detecting a test pattern from the synchronous data repeatedly received a predetermined number of times or more under a mode, and starts an operation upon completion of detection of the test pattern, and compares the synchronous data with the test pattern to generate a comparison signal; A test pattern comparison unit for generating a predetermined pulse signal at each comparison, and an operation when the detection of the test pattern is completed, and a reception data counting unit for counting the pulse signal and counting received data and number of bits. And an error by receiving the comparison signal output from the test pattern comparison unit. An error counting unit for counting the number of bits generated and a bit error rate calculating unit for calculating a bit error rate using the number of received data in units of bits output from the reception data counting unit and the number of errors output from the error counting unit And is mounted on the receiving side.
4. 발명의 중요한 용도4. Important uses of the invention
통신시스템간에 데이타 전송시 그 전송 품질 테스트에 이용할 수 있다.It can be used to test the transmission quality when transferring data between communication systems.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제2도는 본 발명에 따른 피시험장비에 실장될 비트에러율 검출회로의 구성도, 제3도는 제2도 중 비트에러율 검출제어부의 동작을 나타낸 흐름도.2 is a configuration diagram of a bit error rate detection circuit to be mounted in the equipment under test according to the present invention, and FIG. 3 is a flowchart showing the operation of the bit error rate detection control unit in FIG.
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018992A KR970004510A (en) | 1995-06-30 | 1995-06-30 | Mounted bit error rate measuring circuit and its control method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950018992A KR970004510A (en) | 1995-06-30 | 1995-06-30 | Mounted bit error rate measuring circuit and its control method |
Publications (1)
Publication Number | Publication Date |
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KR970004510A true KR970004510A (en) | 1997-01-29 |
Family
ID=66526545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019950018992A KR970004510A (en) | 1995-06-30 | 1995-06-30 | Mounted bit error rate measuring circuit and its control method |
Country Status (1)
Country | Link |
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KR (1) | KR970004510A (en) |
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1995
- 1995-06-30 KR KR1019950018992A patent/KR970004510A/en not_active Application Discontinuation
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