KR960043659A - Interface for I²C Protocol Support - Google Patents

Interface for I²C Protocol Support Download PDF

Info

Publication number
KR960043659A
KR960043659A KR1019950013987A KR19950013987A KR960043659A KR 960043659 A KR960043659 A KR 960043659A KR 1019950013987 A KR1019950013987 A KR 1019950013987A KR 19950013987 A KR19950013987 A KR 19950013987A KR 960043659 A KR960043659 A KR 960043659A
Authority
KR
South Korea
Prior art keywords
data
transmitted
signal
bus
receiver
Prior art date
Application number
KR1019950013987A
Other languages
Korean (ko)
Other versions
KR0143684B1 (en
Inventor
서창원
박용준
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950013987A priority Critical patent/KR0143684B1/en
Publication of KR960043659A publication Critical patent/KR960043659A/en
Application granted granted Critical
Publication of KR0143684B1 publication Critical patent/KR0143684B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

본 발명은 I2C 프로토콜 지원용 인터페이스에 관한 것으로, 데이타를 수신할 경우에는 수신부(10)가 SDA 버스를 통해 전송된 데이타를 수신할 수 있도록 제어하고, SCL버스를 통해 전송된 동기신호를 수신하여 상기 수신부(10)에 수신된 데이타를 상기 동기신호에 동기시켜 입력받아 수신시스템에서 처리할 수 있는 데이타 구조로 변환하는 한편, 데이타를 전송하는경우에는 상기 수신부(10)가 데이타를 수신하지 못하도록 제어하고, SDA 버스를 통해 전송할 데이타 또는 수신응답신호를 전송부(20)로 출력함과 더불어 동기신호를 생성 출력하는 제어부(30): 상기 제어부(30)로부터 인에이블신호를 입력받아상기 전송부(20)에서 출력된 신호를 SDA 버스를 통해 전송하는 제 1 트리스테이트버퍼(40) 및: 상기 제어부(30)로부터 인에이블신호를 입력받아 상기 제어부(30)에서 출력된 동기신호를 SCL버스를 통해 전송하는 제 2 트리스테이트버퍼(50)를포함하여 구성되어, PLD를 사용하여 I2C 프로토콜을 지원할 수 있음에 따라 일반적인 포트를 가지는 디바이스에서 I2C 방식으로 통신할 수 있는 것이다.The present invention relates to an I 2 C protocol support interface, and when receiving data, controls the receiver 10 to receive data transmitted through the SDA bus, and receives a synchronization signal transmitted through the SCL bus. The data received by the receiver 10 is synchronized with the synchronization signal to be converted into a data structure that can be processed by the receiving system, and when the data is transmitted, the receiver 10 controls not to receive the data. The control unit 30 outputs data or a reception response signal to be transmitted through the SDA bus to the transmission unit 20, and generates and outputs a synchronization signal. The controller 30 receives an enable signal from the control unit 30. A first tri-state buffer 40 for transmitting a signal output from 20) through an SDA bus; and receiving the enable signal from the controller 30. It is configured to include a second tree state buffer (50) for transmitting the synchronous signal output from the SCL bus, I 2 C scheme in a device having a general port as it can support the I 2 C protocol using a PLD Can communicate with.

Description

I2C 프로토콜 지원용 인터페이스Interface for I2C Protocol Support

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 I2C 프로토콜 지원용 인터페이스의 구성도이다.2 is a block diagram of an interface for supporting an I 2 C protocol according to the present invention.

Claims (1)

SDA 버스를 통해 전송된 데이타를 수신하는 수신부(10)와; 데이타 또는 수신응답신호를 SDA 버스를 통해 출력하기 위해 직렬 데이타로 변환하는 전송부(20); 데이타를 수신할 경우에는 상기 수신부(10)가 SDA 버스를 통해 전송된 데이타를 수신할 수 있도록 제어하고, SCL 버스를 통해 전송된 동기신호를 수신하여 상기 수신부(10)에 수신된 데이타를 상기 동기신호에 동기시켜 입력받아 수신시스템에서 처리할 수 있는 데이타 구조로 변환하는 한편, 데이타를 전송하는 경우에는 상기 수신부(10)가 데이타를 수신하지 못하도록 제어하고, SDA 버스를 통해 전송할 데이타 또는 수신응답신호를 상기 전송부(20)로 출력함과 더불어 동기신호를 생성 출력하는 제어부(30); 상기 제어부(30)로부터 인에이블신호를 입력받아 상기 전송부(20)에서 출력된 신호를 SDA 버스를 통해 전송하는 한편, 상기 제어부(30)에서 디스인에이블신호가 입력되면 SDA 버스를 통해 전송된 데이타를 수신할 수 있도록 하는 제 1 트리스테이트버퍼(40) 및; 상기 제어부(30)로부터 인에이블신호를 입력받아 상기 제어부(30)에서 출력된 동기신호를 SCL버스를 통해 전송하는 한편, 상기 제어부(30)에서 디스인에이블신호가 입력되면 SCL버스를 통해 전송된 동기신호를 수신할 수 있도록 하는 제 2 트리스테이트버퍼(50)를 포함하여 구성된 I2C 프로토콜 지원용 인터페이스.A receiving unit 10 for receiving data transmitted through the SDA bus; A transmission unit 20 for converting data or a reception response signal into serial data for output through an SDA bus; When receiving data, the receiver 10 controls the receiver 10 to receive data transmitted through the SDA bus, receives a synchronization signal transmitted through the SCL bus, and synchronizes the data received by the receiver 10 with the synchronization. It converts the data into a data structure that can be received in synchronization with the signal and processed by the receiving system. Meanwhile, when data is transmitted, the receiver 10 controls not to receive the data, and transmits data or a response signal to be transmitted through an SDA bus. A control unit 30 for outputting the signal to the transmission unit 20 and generating and outputting a synchronization signal; The enable signal is received from the controller 30, and the signal output from the transmitter 20 is transmitted through an SDA bus. When the disable signal is input from the controller 30, the enable signal is transmitted through the SDA bus. A first tree state buffer (40) for receiving data; The enable signal is received from the controller 30, and the synchronization signal output from the controller 30 is transmitted through the SCL bus. When the disable signal is input from the controller 30, the enable signal is transmitted through the SCL bus. An interface for supporting the I 2 C protocol, including a second tree state buffer (50) for receiving a synchronization signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950013987A 1995-05-30 1995-05-30 An interface for supporting ic protocol KR0143684B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950013987A KR0143684B1 (en) 1995-05-30 1995-05-30 An interface for supporting ic protocol

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950013987A KR0143684B1 (en) 1995-05-30 1995-05-30 An interface for supporting ic protocol

Publications (2)

Publication Number Publication Date
KR960043659A true KR960043659A (en) 1996-12-23
KR0143684B1 KR0143684B1 (en) 1998-08-01

Family

ID=19415973

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950013987A KR0143684B1 (en) 1995-05-30 1995-05-30 An interface for supporting ic protocol

Country Status (1)

Country Link
KR (1) KR0143684B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331105B1 (en) * 2000-03-11 2002-04-06 신현국 Optical communication interface module connected to electrical communication interface module of I2C communication protocol
KR100778476B1 (en) * 2006-02-23 2007-11-21 엘지전자 주식회사 Communication interface converting apparatus and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100331105B1 (en) * 2000-03-11 2002-04-06 신현국 Optical communication interface module connected to electrical communication interface module of I2C communication protocol
KR100778476B1 (en) * 2006-02-23 2007-11-21 엘지전자 주식회사 Communication interface converting apparatus and method thereof

Also Published As

Publication number Publication date
KR0143684B1 (en) 1998-08-01

Similar Documents

Publication Publication Date Title
KR970049636A (en) Data transmission system and method
TW351894B (en) Digital signal link
KR960043659A (en) Interface for I²C Protocol Support
KR970014001A (en) I ^ 2C protocol communication apparatus
KR100260623B1 (en) Received data processing apparatus in optical transmitting system
KR950007335A (en) Serial I / O Interface Device and Method
JP2669844B2 (en) Multiple access control method
KR970031570A (en) A synchronous overhead transmitter of a synchronous transmission system
KR940012139A (en) Bus relay circuit of long distance interface device
KR920005514A (en) Data communication circuit and method of power line transmission module
KR890017905A (en) Personal computer's synchronous / asynchronous modem
KR0169370B1 (en) Signal process circuit of liquid crystal system for data enable signal priority process
KR960040046A (en) TD-bus transmission line reduction method
KR920020863A (en) T1 Stuffing 8B6T Code Converter
KR950033852A (en) Receiver F.F.O buffer matching device in serial communication device
KR950016059A (en) H.D.L.C (HDLC) Communication System Using T1 Transmission Line
KR930022792A (en) Line number expansion circuit by serial-only method of key phone system
KR890011160A (en) Power Control System of Unmanned Relay System
KR930008646A (en) Personal computer serial communication interface
KR900002158A (en) Transmission and reception clock supply method of data terminal device
KR970058078A (en) Communication cable interface device and method
KR970078190A (en) Matching circuit between the SPM device and the PCM
KR970019232A (en) COMPATIBBLE APPARATUS OF UNI GLOBAL BUS
KR970056530A (en) interface
KR940012958A (en) Non-Channel Interface Circuits of Integrated Communication Networks

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010328

Year of fee payment: 4

LAPS Lapse due to unpaid annual fee