KR960043134A - Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof - Google Patents

Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof Download PDF

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Publication number
KR960043134A
KR960043134A KR1019950014292A KR19950014292A KR960043134A KR 960043134 A KR960043134 A KR 960043134A KR 1019950014292 A KR1019950014292 A KR 1019950014292A KR 19950014292 A KR19950014292 A KR 19950014292A KR 960043134 A KR960043134 A KR 960043134A
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KR
South Korea
Prior art keywords
conductive base
intermediate conductive
silicon substrate
semiconductor package
manufacturing
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KR1019950014292A
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Korean (ko)
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KR0142975B1 (en
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정문채
김영대
선용빈
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김광호
삼성전자 주식회사
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Priority to KR1019950014292A priority Critical patent/KR0142975B1/en
Publication of KR960043134A publication Critical patent/KR960043134A/en
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Publication of KR0142975B1 publication Critical patent/KR0142975B1/en

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Abstract

본 발명은 멀티층에 의한 베어칩을 실장공정을 이용하지 않고서도 단일 금속층에 의한 베어칩들의 실장이 가능하도록 하기 위하여, 상술한 바와같이 본 발명에 따른 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지 및 그 제조방법에 의하면, 실리콘 기판의 소정영역에 형성된 적어도 하나 이상의 전극패드와; 상기 전극패드의 사이 사이에 배열 형성되며, 상기 실리콘 기판상에 비 도전성 접착제가 개재되어 다이 본딩된 베어칩들 및 중간 도전성 베이스와; 상기 중간 도전성 베이스 및 전극패드를 매개로 하여 베어칩들의 상호간을 전기적으로 연결하고 있는 적어도 3개 이상의 본딩 와이어로 구성되는 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지 및 그 제조방법에 관한 것이다.The present invention provides a multi-chip semiconductor package using an intermediate conductive base according to the present invention, and the same, in order to be able to mount the bare chips by a single metal layer without using a mounting process for mounting a bare chip by a multi-layer. According to the manufacturing method, at least one electrode pad formed in a predetermined region of the silicon substrate; A bare chip and an intermediate conductive base which are formed between the electrode pads and are die-bonded with a non-conductive adhesive interposed on the silicon substrate; The present invention relates to a multichip semiconductor package using an intermediate conductive base including at least three bonding wires electrically connecting bare chips to each other through the intermediate conductive base and the electrode pad, and a method of manufacturing the same.

Description

중간 도전성 베이스를 이용한 멀티칩 반도체 패키지 및 그 제조방법Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지의 일실시예를 나타낸 단면도, 제3도(가)∼(라)는 본 발명에 따른 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지 제조방법의 일실시예를 나타낸 제조공정도, 제4도는 본 발명에 따른 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지의 회로적인 접속관계를 나타낸 도면이다.2 is a cross-sectional view showing an embodiment of a multi-chip semiconductor package using an intermediate conductive base according to the present invention, Figure 3 (a) to (d) is a method for manufacturing a multi-chip semiconductor package using an intermediate conductive base according to the present invention 4 is a diagram illustrating a circuit connection relationship of a multichip semiconductor package using an intermediate conductive base according to the present invention.

Claims (2)

실리콘 기판의 소정영역에 형성된 적어도 하나 이상의 전극패드와; 상기 전극패드의 사이 사이에 배열 형성되며, 상기 실리콘 기판상에 비도전성 접착제가 개재되어 다이 본딩된 베어칩들 및 중간 도전성 베이스와; 상기 중간도전성 베이스 및 전극패드를 매개로 하여 베어칩들의 상호간을 전기적으로 연결하고 있는 적어도 3개 이상의 본딩 와이어로 구성된 것을 특징으로 하는 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지.At least one electrode pad formed on a predetermined region of the silicon substrate; A bare chip and an intermediate conductive base which are formed between the electrode pads and are die-bonded with a non-conductive adhesive interposed on the silicon substrate; A multi-chip semiconductor package using an intermediate conductive base comprising at least three bonding wires electrically connecting the bare chips to each other through the intermediate conductive base and the electrode pad. 실리콘 기판상에 알루미늄을 침적하여 금속층을 형성하는 단계와; 상기 단계후 , 금속층을 패터닝하여 전극패드를 형성하는 단계와; 상기 결과적 구조상에 비도전성 접착제를 도포한후, 베어칩들과 중간 도전성 베이스를 각각다이 본딩하는 단계와; 상기 단계 후, 베어칩들 및 중간 도전성 베이스의 전극패드와 실리콘 기판상에 형성된 전극패드를 적어도 3번 이상 와이어 본딩하는 단계로 구성된 것을 특징으로 하는 중간 도전성 베이스를 이용한 멀티칩 반도체 패키지의 제조방법.Depositing aluminum on the silicon substrate to form a metal layer; After the step, patterning the metal layer to form an electrode pad; Applying a non-conductive adhesive onto the resulting structure and then die bonding the bare chips and the intermediate conductive base respectively; And after the step, wire bonding at least three times the bare pads and the electrode pads of the intermediate conductive base and the electrode pads formed on the silicon substrate. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950014292A 1995-05-31 1995-05-31 Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof KR0142975B1 (en)

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KR1019950014292A KR0142975B1 (en) 1995-05-31 1995-05-31 Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof

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KR1019950014292A KR0142975B1 (en) 1995-05-31 1995-05-31 Multichip Semiconductor Package Using Intermediate Conductive Base and Manufacturing Method Thereof

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KR960043134A true KR960043134A (en) 1996-12-23
KR0142975B1 KR0142975B1 (en) 1998-07-01

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537893B1 (en) * 1998-11-04 2006-02-28 삼성전자주식회사 Leadframe and multichip package using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100537893B1 (en) * 1998-11-04 2006-02-28 삼성전자주식회사 Leadframe and multichip package using the same

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KR0142975B1 (en) 1998-07-01

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