KR960038621A - Optimal Data Generator for RAM Test - Google Patents

Optimal Data Generator for RAM Test Download PDF

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Publication number
KR960038621A
KR960038621A KR1019950008990A KR19950008990A KR960038621A KR 960038621 A KR960038621 A KR 960038621A KR 1019950008990 A KR1019950008990 A KR 1019950008990A KR 19950008990 A KR19950008990 A KR 19950008990A KR 960038621 A KR960038621 A KR 960038621A
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KR
South Korea
Prior art keywords
ram
data
generator
address
optimal
Prior art date
Application number
KR1019950008990A
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Korean (ko)
Other versions
KR0143131B1 (en
Inventor
김호룡
백상현
김헌철
조창현
Original Assignee
김광호
삼성전자 주식회사
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Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950008990A priority Critical patent/KR0143131B1/en
Publication of KR960038621A publication Critical patent/KR960038621A/en
Application granted granted Critical
Publication of KR0143131B1 publication Critical patent/KR0143131B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1204—Bit line control

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  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

본 발명은 램 테스트를 위한 최적 데이타 발생기에 관한 것으로, 램(15) 위치를 지정하기 위한 번지를 발생시켜 출력하는 번지 발생기(11)와, 멀티플렉서(41)와 시프트 레지스터(42)로 이루어져 있어 데이타 백그라운드를 발생시켜 출력하는 데이타 발생기(40)와; 램(15)으로부터 읽어낸 데이타를 기대하는 패턴과 비교하는 데이타 비교기(13)와; 램 비스트(10)의 전체 흐름을 제어하는 비스트 제어기(14)와; 데이타를 쓸 수도 있고 읽어낼 수도 있는 기능을 갖는 램(15)으로 구성되었으며, 램을 테스트할 때 자체에 내장된 테스트 회로가 차지하는 면적 문제(Area Overhead)와 처리 시간 문제(Time Overhead) 및 데이타 크기에 의존된 회로 구성 문제를 해결하기 위한 램 테스트를 위한 최적 데이타 발생기에 관한 것이다.The present invention relates to an optimal data generator for RAM test, comprising a address generator (11) for generating and outputting a address for designating a RAM (15) position, a multiplexer (41) and a shift register (42). A data generator 40 generating and outputting a background; A data comparator 13 for comparing the data read from the RAM 15 with the expected pattern; A bee controller 14 for controlling the entire flow of the ram bee 10; It consists of RAM (15) that has the ability to write and read data.The area problem, time overhead and data size occupied by its own test circuit when testing RAM. An optimal data generator for RAM testing to solve circuit configuration problems.

Description

램 테스트를 위한 최적 데이타 발생기Optimal Data Generator for RAM Test

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제5도는 본 발명의 실시예에 따른 시프트 레지스터를 이용한 데이타 발생기의 블럭도이고, 제7도는 본 발명의 실시예에 따른 멀티플렉서를 공유한 데이타 발생기의 블럭도이다.5 is a block diagram of a data generator using a shift register according to an embodiment of the present invention, and FIG. 7 is a block diagram of a data generator sharing a multiplexer according to an embodiment of the present invention.

Claims (3)

데이타 백그라운드 인덱스(Data Background Index)와 어드레스 라인(Address Line)을 입력으로 받아, 데이타 백그라운드 인덱스(Data Background Index)에 의해 어드레스 라인(Address Line) 신호를 선택하고, 선택된 어드레스 라인(Address Line) 신호를 한 비트씩 순차적으로 출력하는 선택수단(41)과; 상기 선택수단(41)으로부터 순차적으로 출력되는 한 비트의 어드레스 라인(Address Line) 신호를 입력으로 받아, 순차적으로 시프트시키고 적재함으로써, 원하는 데이타 백그라운드를 생성시켜 램으로 출력하는 시프트레지스터(42)로 이루어지는 것을 특징으로 하는 램 테스트를 위한 최적 데이타 발생기It receives Data Background Index and Address Line as input, selects Address Line signal by Data Background Index, and selects the selected Address Line signal. Selecting means 41 for sequentially outputting bit by bit; It consists of a shift register 42 that receives a bit of an address line signal sequentially output from the selection means 41 as an input, shifts and loads it sequentially, thereby generating a desired data background and outputting it to RAM. Optimal data generator for RAM testing 제1항에 있어서, 상기한 선택수단(41)은, 램 비스트 내부에 데이타 크기가 서로 다른 램이 함께 들어 있는 경우에도 공유해서 사용함으로써, 데이타 크기에 의존된 회로 구성상의 문제를 해결하는 기능을 갖는 멀티플렉서로 이루어지는 것을 특징으로 하는 램 테스트를 위한 최적 데이타 발생기The method according to claim 1, wherein the selecting means (41) uses a function to solve a circuit configuration problem depending on the data size by using the same even when RAMs having different data sizes are included in the RAM Beast. Optimal data generator for RAM testing, characterized in that it comprises a multiplexer with 램 테스트를 하는데 있어서 데이타 백그라운드가 기록될 램(15) 위치를 지정하기 위한 번지를 발생시켜 출력하는 번지 발생기(11)와; 상기 번지 발생기(11)를 통해 지정된 위치에 기록할 데이타 백그라운드를 발생시켜 출력하는 램 테스트를 위한 최적 데이타 발생기(40)와; 램(15)으로부터 읽어낸 데이타를 기대하는 패턴과 비교하는 데이타 비교기(13)와; 램 비스트(10)의 전체 흐름을 제어하는 비스트 제어기(14)와; 데이타를 쓸 수도 있고 읽어낼 수도 있는 기능을 갖는 램(15)으로 이루어지는 것을 특징으로 하는 최적 데이타 발생기로 구현한 램 테스트 회로A address generator 11 which generates and outputs a address for designating a RAM 15 position where a data background is to be recorded in the RAM test; An optimal data generator (40) for RAM testing to generate and output a data background to be recorded at a designated location through the address generator (11); A data comparator 13 for comparing the data read from the RAM 15 with the expected pattern; A bee controller 14 for controlling the entire flow of the ram bee 10; RAM test circuit implemented with an optimal data generator, characterized in that the RAM (15) has a function of writing and reading data
KR1019950008990A 1995-04-17 1995-04-17 Ram test circuit KR0143131B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950008990A KR0143131B1 (en) 1995-04-17 1995-04-17 Ram test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950008990A KR0143131B1 (en) 1995-04-17 1995-04-17 Ram test circuit

Publications (2)

Publication Number Publication Date
KR960038621A true KR960038621A (en) 1996-11-21
KR0143131B1 KR0143131B1 (en) 1998-08-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406556B1 (en) * 2001-06-30 2003-11-22 주식회사 하이닉스반도체 Memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100406556B1 (en) * 2001-06-30 2003-11-22 주식회사 하이닉스반도체 Memory device

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KR0143131B1 (en) 1998-08-17

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